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* sv: Improve testsDavid Shah2019-10-038-7/+30
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Update CHANGELOG and READMEDavid Shah2019-10-032-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add test scripts for typedefsDavid Shah2019-10-035-0/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add %expectDavid Shah2019-10-031-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add support for memories of a typedefDavid Shah2019-10-032-6/+30
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add support for memory typedefsDavid Shah2019-10-033-3/+44
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedefs in packagesDavid Shah2019-10-032-4/+21
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Fix typedef parametersDavid Shah2019-10-034-9/+70
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Switch parser to glr, prep for typedefDavid Shah2019-10-036-11/+111
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16David Shah2019-10-036-2/+184
|\ | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs
| * ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wireEddie Hung2019-10-022-0/+32
|\ \ | | | | | | RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
| * | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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| * | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
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| * | Add testEddie Hung2019-09-301-0/+16
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| * | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* | log_dump() to support State enumEddie Hung2019-10-023-0/+6
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* | Merge pull request #1428 from YosysHQ/clifford/fixbtorClifford Wolf2019-10-021-6/+9
|\ \ | | | | | | Fix btor back-end to use "state" instead of "input" for undef init bits
| * | Fix btor back-end to use "state" instead of "input" for undef init bitsClifford Wolf2019-10-021-6/+9
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1426 from YosysHQ/mmicko/fix_environMiodrag Milanović2019-10-011-0/+2
|\ \ | |/ |/| Define environ, fixes #1424
| * Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
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* Fix typoEddie Hung2019-09-301-1/+1
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* Update doc for equiv_optEddie Hung2019-09-301-2/+3
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* Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-3011-0/+1767
|\ | | | | rpc: new frontend
| * rpc: new frontend.whitequark2019-09-309-0/+744
| | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
| * libs: import json11.whitequark2019-09-303-0/+1023
| | | | | | | | | | This commit imports the code from upstream commit dropbox/json11@8ccf1f0c5ecab6151a65f216e7eeccd8588e5457.
* | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructorsEddie Hung2019-09-301-0/+2
|\ \ | | | | | | Generate Python wrappers for inline constructors
| * | Generate Python wrappers for inline constructorsBenedikt Tutzer2019-09-231-0/+2
| | | | | | | | | | | | Fixes: #1353
* | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-304-6/+10
|\ \ \ | | | | | | | | Open aig frontend as binary file
| * | | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
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| * | | Open aig frontend as binary fileMiodrag Milanovic2019-09-294-5/+5
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* | | | Bump versionClifford Wolf2019-09-301-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2syncClifford Wolf2019-09-301-0/+2
|\ \ \ \ | | | | | | | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosys
| * | | | equiv_opt to call async2sync when not -multiclock like SymbiYosysEddie Hung2019-09-271-0/+2
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* | | | | Merge pull request #1417 from YosysHQ/clifford/fixasync2syncClifford Wolf2019-09-301-0/+1
|\ \ \ \ \ | | | | | | | | | | | | Fix $dlatch handling in async2sync
| * | | | | Fix $dlatch handling in async2syncClifford Wolf2019-09-301-0/+1
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
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* | | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
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* | | | | synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-303-2/+77
| | | | | | | | | | | | | | | | | | | | Fixes #1387.
* | | | | Merge pull request #1414 from hzeller/improve-replace-with-empty-mapEddie Hung2019-09-291-0/+2
|\ \ \ \ \ | | | | | | | | | | | | Avoid work in replace() if rules empty.
| * | | | | Avoid work in replace() if rules empty.Henner Zeller2019-09-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This speeds up processing when number of bits are large but there is actually nothing to replace. Adresses part of #1382. Signed-off-by: Henner Zeller <h.zeller@acm.org>
* | | | | | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2944-281/+6234
|\ \ \ \ \ \ | |_|_|/ / / |/| | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * | | | | Re-orderEddie Hung2019-09-272-2/+2
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| * | | | | Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
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| * | | | | Ooops AREG and BREG to default to -1Eddie Hung2019-09-271-2/+2
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| * | | | | Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
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