iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed comments in manual rtlil/ilang syntax	Clifford Wolf	2013-07-25	1	-2/+1
*	Added RTLIL and Liberty syntax highlighting to manual	Clifford Wolf	2013-07-25	3	-4/+19
*	Automatically run "proc" on extract map files	Clifford Wolf	2013-07-24	1	-0/+5
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23	7	-28/+304
*	Fixed "make clean" for manual files	Clifford Wolf	2013-07-23	1	-1/+1
*	Added web site link to README	Clifford Wolf	2013-07-21	1	-0/+8
*	Added Yosys Manual	Clifford Wolf	2013-07-20	48	-1/+7949
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12	2	-0/+11
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12	2	-2/+10
*	Added ast frontend refactoring to TODO	Clifford Wolf	2013-07-11	1	-0/+1
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11	2	-1/+8
*	Bugfixes for empty signal vectors	Clifford Wolf	2013-07-10	1	-0/+3
*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09	1	-0/+1
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09	2	-22/+23
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09	5	-37/+189
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	5	-37/+189
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09	3	-10/+50
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	2	-1/+11
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07	1	-1/+1
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07	13	-1748/+0
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07	1	-7/+19
*	Fixed handling of $eq and $ne in opt_const	Clifford Wolf	2013-07-07	1	-2/+2
*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05	3	-2/+14
*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05	1	-6/+23
*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05	1	-4/+5
*	Fixed gcc warnings in ezminisat	Clifford Wolf	2013-07-05	1	-2/+2
*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05	1	-0/+13
*	Added xsthammer report generator	Clifford Wolf	2013-07-05	4	-13/+170
*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04	2	-1/+484
*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04	3	-14/+115
*	Documentation updates	Clifford Wolf	2013-07-04	1	-5/+2
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	7	-13/+79
*	Added QMAKE makefile variable	Clifford Wolf	2013-07-03	1	-1/+2
*	Added Altera Quartus support to xsthammer	Clifford Wolf	2013-07-03	3	-2/+39
*	Progress in xsthammer	Clifford Wolf	2013-07-03	5	-9/+23
*	Added vivado support to xsthammer	Clifford Wolf	2013-06-26	5	-7/+69
*	Added SAT support for -all/-max with -verify	Clifford Wolf	2013-06-23	1	-6/+11
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-20	1	-2/+28
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\| *	Added renaming of wires and cells to "rename" command	Clifford Wolf	2013-06-19	1	-2/+28
* \|	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20	6	-8/+120
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*	Added "eval" pass	Clifford Wolf	2013-06-19	6	-189/+316
*	Fixed build with clang	Clifford Wolf	2013-06-18	1	-41/+69
*	Added splitnets command	Clifford Wolf	2013-06-18	2	-0/+110
*	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	Clifford Wolf	2013-06-18	2	-2/+79
*	Added more stuff to xsthammer, found first xst bug	Clifford Wolf	2013-06-17	2	-2/+175
*	Added support for "assign" statements in abc vlparse	Clifford Wolf	2013-06-15	2	-2/+39
*	Added ternary op and concat op to xsthammer	Clifford Wolf	2013-06-15	1	-7/+124
*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14	3	-30/+59
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13	3	-2/+112
*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13	6	-70/+50