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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-11 19:31:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-11 19:31:57 +0200 |
| commit | 3cd97a205f30e9c0671b3a909f3371fe02e0f0b2 (patch) | |
| tree | c359401b1e8db32c99708e306f6cfaf23d3aac1e | |
| parent | b380c8c790233f9237b503656cfd28fd5e65eff5 (diff) | |
| download | yosys-3cd97a205f30e9c0671b3a909f3371fe02e0f0b2.tar.gz yosys-3cd97a205f30e9c0671b3a909f3371fe02e0f0b2.tar.bz2 yosys-3cd97a205f30e9c0671b3a909f3371fe02e0f0b2.zip | |
Added ast frontend refactoring to TODO
| -rw-r--r-- | README | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -259,4 +259,5 @@ TODOs / Open Bugs - Additional internal cell types: $pla and $lut - Support for registering designs (as collection of modules) to CellTypes - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) + - Refactoring of AST frontend (clean expr width/sign code, AST passes) |