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* Fix use-after-free in LUT opt passStefanBruens2020-12-221-2/+4
| | | | | RTLIL::Module::remove(Cell* cell) calls `delete cell`. Any subsequent accesses of `cell` then causes undefined behavior.
* Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-222-0/+14
|\ | | | | Allow constant function calls in constant function arguments
| * Allow constant function calls in constant function argumentsZachary Snow2020-12-072-0/+14
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* | Merge pull request #2491 from zachjs/port-bind-signwhitequark2020-12-225-5/+132
|\ \ | | | | | | Sign extend port connections where necessary
| * | Sign extend port connections where necessaryZachary Snow2020-12-185-5/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* | | Bump versionYosys Bot2020-12-221-1/+1
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* | | xilinx: Add some missing blackbox cells.Marcelina Kościelnicka2020-12-213-798/+6276
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* | | xilinx: Regenerate cells_xtra.v using Vivado 2020.2Marcelina Kościelnicka2020-12-212-42/+49
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* | | Merge pull request #2496 from whitequark/cxxrtl-fixeswhitequark2020-12-213-9/+32
|\ \ \ | | | | | | | | cxxrtl: various improvements
| * | | cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-212-5/+28
| | | | | | | | | | | | | | | | | | | | On Minerva SoC SRAM, depending on the compiler, this change improves overall time by 4-7%.
| * | | cxxrtl: speed up commits on clang.whitequark2020-12-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | On Minerva SoC SRAM compiled with clang-11, this change cuts commit time in half (!) and overall time by 20%. When compiled with gcc-10, there is no difference.
| * | | cxxrtl: use `static inline` instead of `inline` in the C API.whitequark2020-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In C, non-static inline functions require an implementation elsewhere (even though the body is right there in the header). It is basically never desirable to use those as opposed to static inline ones.
* | | | Bump versionYosys Bot2020-12-201-1/+1
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* | | Merge pull request #2487 from whitequark/cxxrtl-outliningwhitequark2020-12-196-169/+415
|\ \ \ | | | | | | | | CXXRTL: implement zero-cost full coverage debug information through the magic✨ of outlining🪄🎀🧹
| * | | cxxrtl: print names of cells inlined in connections.whitequark2020-12-151-1/+10
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| * | | cxxrtl: disable optimization of debug_items().whitequark2020-12-152-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementing outlining has greatly increased the amount of debug information in a typical build, and consequently exposed performance issues in C++ compilers, which are similar for both GCC and Clang; the compile time of Minerva SoC SRAM increased almost twofold. Although one would expect the slowdown to be caused by the increased use of templates in `debug_eval()`, it is actually almost entirely attributable to optimizations and codegen for `debug_items()`. Fortunately, it is neither possible nor desirable to optimize `debug_items()`: in most cases it is called exactly once, and its body is a linear sequence of calls with unique arguments. This commit turns off optimizations for `debug_items()` on GCC and Clang, improving -Os compile time of Minerva SoC SRAM by ~40% (!)
| * | | cxxrtl: make alias analysis outlining-aware.whitequark2020-12-151-38/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, if a sequence of wires assigned in a chain would terminate on a cell, none of the wires would get marked as aliases, and typically all of the public wires would get outlined. The reason for this behavior is that alias analysis predates outlining and in fact runs before it. After this commit, alias analysis runs after outlining and considers outlined wires valid aliasees. More importantly, if the chained wires contain any valid aliasees, then all of the wires are aliased to the one that is topologically deepest. Aliased wires incur virtually no overhead for the VCD writer, unlike outlined wires that would otherwise take their place. On Minerva SoC SRAM, size of the full VCD dump is reduced by ~65%, and throughput is increased by ~55%.
| * | | cxxrtl: add a "bare minimum" debug information level.whitequark2020-12-141-9/+17
| | | | | | | | | | | | | | | | | | | | Useful to reduce overhead when no debug capabilities are necessary except for access to design state.
| * | | cxxrtl: implement debug information outlining.whitequark2020-12-145-71/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aggressive wire localization and inlining is necessary for CXXRTL to achieve high performance. However, that comes with a cost: reduced debug information coverage. Previously, as a workaround, the `-Og` option could have been used to guarantee complete coverage, at a cost of a significant performance penalty. This commit introduces debug information outlining. The main eval() function is compiled with the user-specified optimization settings. In tandem, an auxiliary debug_eval() function, compiled from the same netlist, can be used to reconstruct the values of localized/inlined signals on demand. To the extent that it is possible, debug_eval() reuses the results of computations performed by eval(), only filling in the missing values. Benchmarking a representative design (Minerva SoC SRAM) shows that: * Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%. * Switching from `-g1` to `-g2`, both used with `-O6`, increases compile time by ~25%. * Although `-g2` increases the resident size of generated modules, this has no effect on runtime. Because the impact of `-g2` is minimal and the benefits of having unconditional 100% debug information coverage (and the performance improvement as well) are major, this commit removes `-Og` and changes the defaults to `-O6 -g2`. We'll have our cake and eat it too!
| * | | cxxrtl: rename "elision" to "inlining". NFC.whitequark2020-12-131-77/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "Elision" in this context is an unusual and not very descriptive term whereas "inlining" is common and straightforward. Also, introducing "inlining" makes it easier to introduce its dual under the obvious name "outlining".
| * | | cxxrtl: fix outdated comment. NFC.whitequark2020-12-131-2/+2
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| * | | cxxrtl: use IdString::isPublic(). NFC.whitequark2020-12-131-4/+4
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| * | | kernel: make IdString::isPublic() const.whitequark2020-12-121-1/+1
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* | | | Bump versionYosys Bot2020-12-181-1/+1
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* | | | xilinx: Add FDDRCPE and FDDRRSE blackbox cells.Marcelina Kościelnicka2020-12-172-0/+33
| |/ / |/| | | | | | | | | | | These are necessary primitives for proper DDR support on Virtex 2 and Spartan 3.
* | | Bump versionYosys Bot2020-12-151-1/+1
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* | | timinginfo: Error instead of segfault on const signals.Marcelina Kościelnicka2020-12-151-2/+2
| | | | | | | | | | | | Reported by @Ravenslofty
* | | Bump versionYosys Bot2020-12-131-1/+1
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* | Merge pull request #2485 from whitequark/cxxrtl-cell-input-bufferingwhitequark2020-12-122-25/+33
|\ \ | | | | | | cxxrtl: don't overwrite buffered inputs
| * | cxxrtl: don't overwrite buffered inputs.whitequark2020-12-112-25/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, a cell's input was always assigned like: p_cell.p_input = (value...); If `p_input` is buffered (e.g. if the design is built at -O0), this is not correct. (In practice, this breaks clocking.) Unfortunately, the incorrect design was compiled without diagnostics because wire<> was move-assignable and also implicitly constructible from value<>. After this commit, cell inputs are no longer incorrectly assumed to always be unbuffered, and wires are not assignable from values.
* | | Bump versionYosys Bot2020-12-101-1/+1
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* | | Merge pull request #2483 from YosysHQ/pmgen_nice_errorMiodrag Milanović2020-12-091-2/+6
|\ \ \ | | | | | | | | Return nice error in pmgen generated code, fixes #2482
| * | | Return nice error in pmgen generated code, fixes #2482Miodrag Milanovic2020-12-091-2/+6
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* / / Bump versionYosys Bot2020-12-091-1/+1
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* | Merge pull request #2478 from whitequark/improve-bugpointwhitequark2020-12-082-19/+101
|\ \ | |/ |/| bugpoint: various improvements
| * bugpoint: add -wires option.whitequark2020-12-072-4/+39
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| * bugpoint: try to remove whole processes first.whitequark2020-12-071-4/+40
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| * bugpoint: accept quoted strings in -grep.whitequark2020-12-071-1/+4
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| * bugpoint: add -command option.whitequark2020-12-071-13/+21
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* Bump versionYosys Bot2020-12-041-1/+1
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* Merge pull request #2470 from whitequark/cxxrtl-create_atwhitequark2020-12-032-1/+20
|\ | | | | cxxrtl: allow customizing the root module path in the C API
| * cxxrtl: allow customizing the root module path in the C API.whitequark2020-12-032-1/+20
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* Bump versionYosys Bot2020-12-031-1/+1
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* Merge pull request #2468 from whitequark/cxxrtl-assertwhitequark2020-12-022-2/+16
|\ | | | | cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert
| * cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert.whitequark2020-12-022-2/+16
| | | | | | | | | | | | | | | | RTL contract violations and C++ contract violations are different: the former depend on the netlist and will never violate memory safety whereas the latter may. When loading a CXXRTL simulation into another process, RTL contract violations should generally not crash it, while C++ contract violations should.
* | Merge pull request #2469 from whitequark/cxxrtl-no-clkwhitequark2020-12-021-6/+14
|\ \ | | | | | | cxxrtl: fix crashes caused by a floating or constant clock input
| * | cxxrtl: fix crashes caused by a floating or constant clock input.whitequark2020-12-021-6/+14
| |/ | | | | | | | | | | | | | | | | | | | | E.g. in: module test; wire clk = 0; reg data; always @(posedge clk) data <= 0; endmodule
* | Merge pull request #2466 from whitequark/cxxrtl-resetwhitequark2020-12-024-3/+78
|\ \ | | | | | | cxxrtl: provide a way to perform unobtrusive power-on reset
| * | cxxrtl: provide a way to perform unobtrusive power-on reset.whitequark2020-12-024-3/+78
| |/ | | | | | | | | | | | | | | | | | | | | Although it is always possible to destroy and recreate the design to simulate a power-on reset, this has two drawbacks: * Black boxes are also destroyed and recreated, which causes them to reacquire their resources, which might be costly and/or erase important state. * Pointers into the design are invalidated and have to be acquired again, which is costly and might be very inconvenient if they are captured elsewhere (especially through the C API).
* | Merge pull request #2456 from Zottel/masterwhitequark2020-12-021-0/+1
|\ \ | | | | | | Return correct modname when found in cache.
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