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author | whitequark <whitequark@whitequark.org> | 2020-12-15 03:46:06 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2020-12-15 11:02:38 +0000 |
commit | d889a3df35e539b6dcfbee9c6a98461eca1a0b0e (patch) | |
tree | 671f162b4944a1a4ed602bb85ba94f149a462170 | |
parent | f75bc6c7aac92c7c1c8954ec7fe5325a94e6e491 (diff) | |
download | yosys-d889a3df35e539b6dcfbee9c6a98461eca1a0b0e.tar.gz yosys-d889a3df35e539b6dcfbee9c6a98461eca1a0b0e.tar.bz2 yosys-d889a3df35e539b6dcfbee9c6a98461eca1a0b0e.zip |
cxxrtl: print names of cells inlined in connections.
-rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 7bf44626a..9875aba60 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -911,7 +911,16 @@ struct CxxrtlWorker { if (for_debug && !is_connect_outlined(conn)) return; - f << indent << "// connection\n"; + std::vector<RTLIL::IdString> inlined_cells; + collect_sigspec_rhs(conn.second, inlined_cells); + if (for_debug || inlined_cells.empty()) { + f << indent << "// connection\n"; + } else { + f << indent << "// cells"; + for (auto inlined_cell : inlined_cells) + f << " " << inlined_cell.str(); + f << "\n"; + } f << indent; dump_sigspec_lhs(conn.first, for_debug); f << " = "; |