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| author | whitequark <whitequark@whitequark.org> | 2020-12-02 22:20:02 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-02 22:20:02 +0000 |
| commit | 90724ea9e7bc5872dd8412521399221722756c4e (patch) | |
| tree | 8ab22eb51a82ce3567c24d1d017be10ea0f026e1 | |
| parent | 975b2d4283dcdc541d9fadbbd0e8269ef14ff265 (diff) | |
| parent | 2e23dfd96bee8df01912ffae71b95aaf35567aa7 (diff) | |
| download | yosys-90724ea9e7bc5872dd8412521399221722756c4e.tar.gz yosys-90724ea9e7bc5872dd8412521399221722756c4e.tar.bz2 yosys-90724ea9e7bc5872dd8412521399221722756c4e.zip | |
Merge pull request #2456 from Zottel/master
Return correct modname when found in cache.
| -rw-r--r-- | frontends/ast/ast.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index c8183580b..1c0a8b34d 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1511,6 +1511,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr } } else { + modname = new_modname; log("Found cached RTLIL representation for module `%s'.\n", modname.c_str()); } |