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* cxxrtl: run edge detectors only once in eval().whitequark2020-04-221-6/+22
| | | | As a result, Minerva SRAM SoC runs ~15% faster.
* cxxrtl: add an unsupported knob for manipulating clock trees.whitequark2020-04-221-0/+18
| | | | | | | | | This is quite possibly the worst way to implement this, but it does work for a subset of well-behaved designs, and can be used to measure how much performance is lost simulating the inactive edge of a clock. It should be replaced with a clock tree analyzer generating safe code once it is clear how should such a thing look like.
* cxxrtl: use log_id() where appropriate. NFC.whitequark2020-04-211-4/+4
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* cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.whitequark2020-04-211-65/+186
| | | | | | | | | | | | | | | | | | | | | | If the annotations are not used, this commit does not alter semantics at all, other than removing elision of outputs of black box cells. (Elision of such outputs is expected to be too rare to have any noticeable benefit, and the implementation was somewhat of a hack.) The (* cxxrtl.comb *) annotation alters the semantics of the output of the black box it is applied to such that, if the black box converges immediately, no additional delta cycle is necessary to propagate the computed combinatorial value upwards in hierarchy. The (* cxxrtl.sync *) annotation alters the semantics of the output of the black box it is applied to such as to remove any uses of the black box by the wires connected to this output, and break false feedback arcs arising from conservative modeling of dependencies of the black box. Although currently these attributes are only recognized on black boxes, if separate compilation is added in the future, it could also emit and consume them.
* cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.whitequark2020-04-211-23/+23
| | | | | | | The attribute for this is called (* cxxrtl.edge *), and there is a planned attribute (* cxxrtl.sync *) that would cause blackbox cell outputs to be added to sync defs rather than comb defs. Rename the edge detector related stuff to avoid confusion.
* cxxrtl: use one delta cycle for immediately converging netlists.whitequark2020-04-212-11/+21
| | | | | | | | | | | If it is statically known that eval() will converge in one delta cycle (that is, the second commit() will always return `false`) because the design contains no feedback or buffered wires, then there is no need to run the second delta cycle at all. After this commit, the case where eval() always converges immediately is detected and the second delta cycle is omitted. As a result, Minerva SRAM SoC runs ~25% faster.
* cxxrtl: add -O6, a shortcut for running `proc; flatten`.whitequark2020-04-211-4/+14
| | | | | | | People judge a compiler backend by the first impression, and the metric they judge it for is speed. -O6 does severely impact debuggability, but it provides equally massive gains in performance, so use it by default.
* cxxrtl: unbuffer module input wires.whitequark2020-04-211-31/+61
| | | | | | | | Module input wires are never set by the module, so it is unnecessary to buffer them. Although important for all inputs, this is especially critical for clocks, since after this commit, hierarchy levels no longer add delta cycles. As a result, Minerva SRAM SoC runs ~73% faster when flattened, and ~264% (!!) faster when hierarchical.
* cxxrtl: simplify generated edge detection logic.whitequark2020-04-211-56/+29
| | | | | | | | | This commit changes the way edge detectors are represented in generated code from a variable that is set in commit() and reset in eval() to a function that considers .curr and .next of the clock wire. Behavior remains the same. Besides being simpler to generate and providing more opportunities for optimization, this commit paves way for unbuffering module inputs.
* cxxrtl: localize wires with multiple comb drivers, too.whitequark2020-04-211-32/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, any wire that was not driven by an output port of exactly one comb cell would not be localized, even if there were no feedback arcs through that wire. This would cause the wire to become buffered and require (often quite a few) extraneous delta cycles during evaluation. To alleviate this problem, -O5 was running `splitnets -driver`. However, this solution was mistaken. Because `splitnets -driver` followed by `opt_clean -purge` would produce more nets with multiple drivers, it would have to be iterated to fixpoint. Moreover, even if this was done, it would not be sufficient because `opt_clean -purge` does not currently remove wires with the `\init` attribute (and it is not desirable to remove such wires, since they correspond to registers and may be useful for debugging). The proper solution is to consider the condition in which a wire may be localized. Specifically, if there are no feedback arcs through this wire, and no part of the wire is driven by an output of a sync cell, then the wire holds no state and is localizable. After this commit, the original condition for not localizing a wire is replaced by a check for any sync cell driving it. This makes it unnecessary to run `splitnets -driver` in the majority of cases to get a design with no buffered wires, and -O5 no longer includes that pass. As a result, Minerva SRAM SoC no longer has any buffered wires, and runs ~27% faster. In addition, this commit prepares the flow graph for introduction of sync outputs of black boxes. Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
* cxxrtl: detect buffered comb wires, not just feedback wires.whitequark2020-04-211-5/+40
| | | | | | | | | | Any buffered combinatorial wires (including, as a subset, feedback wires) will prevent the design from always converging in one delta cycle. Before this commit, only feedback wires were detected. After this commit, any buffered combinatorial wires, including feedback wires, are detected. Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
* Merge pull request #1961 from whitequark/paramod-original-namewhitequark2020-04-213-11/+7
|\ | | | | ast, rpc: record original name of $paramod\* as \hdlname attribute
| * ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-183-11/+7
| | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* | tests: remove write_ilangEddie Hung2020-04-202-3/+0
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* | Merge pull request #1972 from YosysHQ/eddie/bug1970Eddie Hung2020-04-202-16/+52
|\ \ | | | | | | abc9_ops: -prep_lut to be more robust
| * | abc9: -prep_lut to be more robustEddie Hung2020-04-201-16/+33
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| * | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | Merge pull request #1964 from YosysHQ/claire/sformatfClaire Wolf2020-04-201-8/+38
|\ \ | | | | | | Extend support for format strings in Verilog front-end
| * | Extend support for format strings in Verilog front-endClaire Wolf2020-04-181-8/+38
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #1967 from whitequark/cxxrtl-blackbox-attributeswhitequark2020-04-192-49/+57
|\ \ \ | |/ / |/| | cxxrtl: provide attributes to black box factories, too
| * | cxxrtl: provide attributes to black box factories, too.whitequark2020-04-192-49/+57
|/ / | | | | | | | | | | | | | | | | Both parameters and attributes are necessary because the parameters have to be the same between every instantiation of the cell, but attributes may well vary. For example, for an UART PHY, the type of the PHY (tty, pty, socket) would be a parameter, but configuration of the implementation specified by the type (socket address) would be an attribute.
* | Merge pull request #1963 from whitequark/cxxrtl-blackboxeswhitequark2020-04-182-198/+637
|\ \ | | | | | | cxxrtl: add support for simple and templated C++ black boxes
| * | cxxrtl: add templated black box support.whitequark2020-04-181-16/+193
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| * | cxxrtl: make eval() and commit() inline in blackboxes.whitequark2020-04-181-82/+103
| | | | | | | | | | | | | | | This change is a preparation for template blackboxes. It has no effect on current generated code.
| * | cxxrtl: add simple black box support.whitequark2020-04-182-70/+311
| | | | | | | | | | | | | | | | | | | | | This commit adds support for replacing RTLIL modules with CXXRTL black boxes. Black box port widths may not depend on the parameters with which it is instantiated (yet); the parameters may only be used to change the behavior of the black box.
| * | cxxrtl: use ID::X instead of ID(X). NFC.whitequark2020-04-181-107/+107
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* | Merge pull request #1955 from whitequark/cxxrtl-sync_alwayswhitequark2020-04-171-3/+13
|\ \ | | | | | | cxxrtl: correctly handle `sync always` rules
| * | cxxrtl: correctly handle `sync always` rules.whitequark2020-04-171-3/+13
| |/ | | | | | | Fixes #1948.
* | Merge pull request #1952 from boqwxp/add_edge_locationwhitequark2020-04-171-0/+3
|\ \ | |/ |/| Verilog frontend: add source location in more parser rules
| * Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
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| * Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵Alberto Gonzalez2020-04-171-0/+2
| | | | | | | | nodes.
* | Merge pull request #1954 from YosysHQ/dave/fix-stdout-conflictwhitequark2020-04-171-3/+3
|\ \ | | | | | | qbfsat: Fix illegal use of 'stdout' identifier
| * | qbfsat: Fix illegal use of 'stdout' identifierDavid Shah2020-04-171-3/+3
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1951 from whitequark/rtlil-string_attributewhitequark2020-04-172-19/+33
|\ \ | |/ |/| rtlil: add AttrObject::{get,set}_string_attribute, AttrObject::has_attribute
| * rtlil: add AttrObject::has_attribute.whitequark2020-04-162-0/+7
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| * rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-162-19/+26
| | | | | | | | And make {get,set}_src_attribute use those functions.
* | Merge pull request #1898 from boqwxp/locationswhitequark2020-04-171-0/+3
|\ \ | | | | | | Verilog frontend: add location information to parsed constants
| * | Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
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* | | Merge pull request #1864 from boqwxp/cleanup_techmap_abcwhitequark2020-04-171-99/+80
|\ \ \ | | | | | | | | Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`
| * | | Simplify `passes/techmap/abc.cc` and remove superfluous `RTLIL::SigSpec` ↵Alberto Gonzalez2020-04-141-132/+49
| | | | | | | | | | | | | | | | | | | | | | | | constructions. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`.Alberto Gonzalez2020-04-051-99/+163
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* | | | Merge pull request #1888 from boqwxp/cleanup_scatterwhitequark2020-04-171-17/+11
|\ \ \ \ | | | | | | | | | | Clean up `passes/cmds/scatter.cc`.
| * | | | Replace `std::map` with `dict`.Alberto Gonzalez2020-04-161-2/+2
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | Replace pseudo-private member access to `connections_` in ↵Alberto Gonzalez2020-04-161-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `passes/cmds/scatter.cc`. Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | | Clean up `passes/cmds/scatter.cc`.Alberto Gonzalez2020-04-161-10/+7
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* | | | Merge pull request #1882 from boqwxp/cleanup_renamewhitequark2020-04-171-119/+103
|\ \ \ \ | | | | | | | | | | Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
| * | | | Use `dict` instead of `std::map`.Alberto Gonzalez2020-04-161-9/+9
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | Revert to `stringf()` rather than stringstreams.Alberto Gonzalez2020-04-161-12/+8
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| * | | | Clean up pseudo-private member usage in `passes/cmds/rename.cc`.Alberto Gonzalez2020-04-161-119/+107
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* | | | Merge pull request #1929 from YosysHQ/eddie/select_unsetwhitequark2020-04-164-3/+43
|\ \ \ \ | |_|_|/ |/| | | select: add select -unset option
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