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author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-13 19:37:01 +0000 |
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committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-16 18:49:55 +0000 |
commit | ff8be2364e9d9aecb084f7fff07a2538b5e6d02e (patch) | |
tree | 5fd374c2c878ce2a3a1e05d9ce686464ba7662fe | |
parent | 0424555702de0c17841d8306f734faa788bc504d (diff) | |
download | yosys-ff8be2364e9d9aecb084f7fff07a2538b5e6d02e.tar.gz yosys-ff8be2364e9d9aecb084f7fff07a2538b5e6d02e.tar.bz2 yosys-ff8be2364e9d9aecb084f7fff07a2538b5e6d02e.zip |
Replace `std::map` with `dict`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
-rw-r--r-- | passes/cmds/scatter.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index cd1b3286f..a5ef95f02 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -49,9 +49,9 @@ struct ScatterPass : public Pass { for (auto module : design->selected_modules()) { for (auto cell : module->cells()) { - std::map<RTLIL::IdString, std::pair<RTLIL::SigSpec, RTLIL::SigSpec>> new_connections; + dict<RTLIL::IdString, RTLIL::SigSig> new_connections; for (auto conn : cell->connections()) - new_connections.emplace(conn.first, std::make_pair(conn.second, module->addWire(NEW_ID, conn.second.size()))); + new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second)))); for (auto &it : new_connections) { if (ct.cell_output(cell->type, it.first)) module->connect(RTLIL::SigSig(it.second.first, it.second.second)); |