iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| * \|	Merge pull request #5 from hansiglaser/master	Clifford Wolf	2013-04-05	1	-6/+23
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\| \| * \|	fsm_export: optionally use binary state encoding as state names instead of	Johann Glaser	2013-04-05	1	-6/+23
\| * \| \|	Merge pull request #4 from hansiglaser/master	Clifford Wolf	2013-04-05	1	-5/+20
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\| \| * \|	fsm_export: specify KISS filename on command line	Johann Glaser	2013-04-05	1	-5/+20
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* / /	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	Clifford Wolf	2013-04-07	1	-4/+4
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* \|	Fixed/improved handling of colored wires in show command	Clifford Wolf	2013-04-01	1	-2/+2
* \|	Added support for @<set-name> in expand select ops (%x, %ci, %co)	Clifford Wolf	2013-04-01	1	-2/+12
* \|	Removed 4096 bytes limit for size of command from script file	Clifford Wolf	2013-04-01	1	-3/+20
* \|	Added -color <color> <selection> option to show command	Clifford Wolf	2013-04-01	4	-22/+101
* \|	Fixed "select" for "%%" stmt with emty stack	Clifford Wolf	2013-03-31	1	-1/+2
* \|	Added "script" command	Clifford Wolf	2013-03-31	1	-0/+16
* \|	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	5	-21/+32
* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	5	-3/+15
* \|	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	Clifford Wolf	2013-03-31	6	-0/+111
* \|	Added k68 (m68k compatible cpu) test case from verilator	Clifford Wolf	2013-03-31	3	-0/+61
* \|	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29	3	-3/+32
* \|	Improved opt_share for commutative standard cells	Clifford Wolf	2013-03-29	1	-1/+28
* \|	Added EXTRA_TARGETS Makefile variable	Clifford Wolf	2013-03-28	2	-2/+3
* \|	Improved Makefile: Added ENABLE_* switches	Clifford Wolf	2013-03-28	1	-8/+24
* \|	Implemented TCL support (only via -c option at the moment)	Clifford Wolf	2013-03-28	5	-9/+83
* \|	Improved subcircuit verbose output (added portmapper results)	Clifford Wolf	2013-03-28	1	-0/+15
* \|	Fixed svgviewer hacks for builtin files	Clifford Wolf	2013-03-28	1	-8/+9
* \|	Added proper TECHMAP_FAIL support and added support for the celltype attribut...	Clifford Wolf	2013-03-28	1	-84/+129
* \|	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	7	-16/+70
* \|	Keep viewport transform stable on reload in yosys-svgviewer	Clifford Wolf	2013-03-27	2	-4/+8
* \|	Added check: only one module for "show" unless format is "ps"	Clifford Wolf	2013-03-27	1	-0/+9
* \|	Now using SVG and yosys-svgviewer per default in show command	Clifford Wolf	2013-03-27	4	-16/+67
* \|	Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib	Clifford Wolf	2013-03-27	4	-5/+18
* \|	Imported svgviewer from qt4.8	Clifford Wolf	2013-03-27	11	-0/+994
* \|	Create nice errors when calling RTLIL::Module::derive() of base class	Clifford Wolf	2013-03-26	1	-3/+3
* \|	Collect parameters in hierarchy -generate (and do nothing with them)	Clifford Wolf	2013-03-26	1	-1/+8
* \|	Tiny bugfix in simlib.v	Clifford Wolf	2013-03-26	1	-1/+0
* \|	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	2	-4/+2
* \|	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	2	-1/+19
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	5	-34/+27
*	Improved verbose output of subcircuit	Clifford Wolf	2013-03-25	1	-1/+11
*	Improved method for finding fsm_expand candidates	Clifford Wolf	2013-03-25	1	-5/+7
*	Added hierarchy -generate command for generating skeletton modules	Clifford Wolf	2013-03-25	2	-4/+172
*	Changed fsm_expand to merge multiplexers more aggressively	Clifford Wolf	2013-03-24	1	-1/+4
*	Renamed hansimem.v test case to mem_arst.v	Clifford Wolf	2013-03-24	1	-1/+0
*	Fixed handling of show -viewer	Clifford Wolf	2013-03-24	1	-1/+1
*	Fixed handling of internal signals in show command	Clifford Wolf	2013-03-24	1	-2/+2
*	Improved show -colors color assignments	Clifford Wolf	2013-03-24	1	-2/+3
*	Added show -strech and renamed -widthlabels to -width	Clifford Wolf	2013-03-24	1	-6/+36
*	Added -widthlabels options to chow command	Clifford Wolf	2013-03-24	1	-31/+67
*	Added -notypes option to intersynth backend	Clifford Wolf	2013-03-24	1	-7/+18
*	Reorganized TODOs	Clifford Wolf	2013-03-24	1	-24/+13
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	5	-11/+31
*	Fixed stdcells.v for $adff with undef reset value	Clifford Wolf	2013-03-24	1	-63/+68
*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24	1	-1/+3