iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added $meminit test case	Clifford Wolf	2015-02-14	1	-0/+30
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*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	5	-7/+34
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*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14	4	-33/+57
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*	Added $meminit cell type	Clifford Wolf	2015-02-14	4	-1/+33
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*	Fixed handling of "//" in filenames in verilog pre-processor	Clifford Wolf	2015-02-14	2	-1/+5
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*	Fixed "write_verilog -attr2comment" handling of "*/" in strings	Clifford Wolf	2015-02-13	1	-2/+4
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*	hotfix in "check" command	Clifford Wolf	2015-02-13	1	-1/+2
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*	Added "check" command	Clifford Wolf	2015-02-13	3	-0/+131
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*	Added AstNode::simplify() recursion counter	Clifford Wolf	2015-02-13	1	-2/+10
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*	Added EMCCFLAGS	Clifford Wolf	2015-02-13	1	-0/+8
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*	Some test related fixes	Clifford Wolf	2015-02-12	6	-156/+6
\| \| \| \|	(incl. removal of three bad test cases)
*	Added "proc_dlatch"	Clifford Wolf	2015-02-12	3	-1/+311
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*	Less aggressive "share" defaults	Clifford Wolf	2015-02-10	1	-4/+6
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*	Improved read_verilog support for empty behavioral statements	Clifford Wolf	2015-02-10	1	-6/+2
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*	Added "scc -expect <N> -nofeedback"	Clifford Wolf	2015-02-10	1	-7/+48
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*	Some hashlib improvements	Clifford Wolf	2015-02-09	1	-9/+37
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*	Various changes to release checklist	Clifford Wolf	2015-02-09	2	-45/+28
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*	Fixed creation of command reference in manual	Clifford Wolf	2015-02-09	3	-9/+16
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*	We are now in 0.5+ development	Clifford Wolf	2015-02-09	1	-1/+1
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*	Yosys 0.5	Clifford Wolf	2015-02-09	1	-1/+1
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*	Bugfix in "make vcxsrc"	Clifford Wolf	2015-02-09	1	-1/+1
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*	Updated command reference in manual	Clifford Wolf	2015-02-09	1	-75/+440
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*	Various presentation fixes	Clifford Wolf	2015-02-09	2	-8/+15
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*	Fixed iterator invalidation bug in "rename" command	Clifford Wolf	2015-02-09	1	-3/+4
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*	CodingReadme update	Clifford Wolf	2015-02-08	1	-0/+1
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*	Fixed bug in "show -format .."	Clifford Wolf	2015-02-08	1	-1/+1
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*	Added new APIs to changelog	Clifford Wolf	2015-02-08	1	-0/+1
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*	Fixed eval_select_op() api	Clifford Wolf	2015-02-08	2	-2/+2
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*	Added eval_select_args() and eval_select_op()	Clifford Wolf	2015-02-08	2	-4/+29
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*	Minor "make vgtest" changes	Clifford Wolf	2015-02-08	2	-2/+6
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*	Various ModIndex improvements	Clifford Wolf	2015-02-08	1	-13/+54
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*	Added Yosys 0.5 Changelog	Clifford Wolf	2015-02-08	1	-4/+46
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*	Various updates to CodingReadme	Clifford Wolf	2015-02-08	1	-10/+13
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*	Added equiv_add	Clifford Wolf	2015-02-08	2	-0/+90
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*	Ignore explicit assignments to constants in HDL code	Clifford Wolf	2015-02-08	1	-0/+14
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*	Fixed a bug with autowire bit size	Clifford Wolf	2015-02-08	1	-9/+3
\| \| \| \|	(removed leftover from when we tried to auto-size the wires)
*	fixed typo	Clifford Wolf	2015-02-08	1	-1/+1
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*	Added "yosys-config --build modname.so cppsources.."	Clifford Wolf	2015-02-08	1	-2/+12
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*	Added SigSpec::has_const()	Clifford Wolf	2015-02-08	2	-0/+13
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*	Cleanup in add_share_file make macro	Clifford Wolf	2015-02-08	1	-3/+3
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*	Removed "make mklibyosys"	Clifford Wolf	2015-02-07	1	-14/+0
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*	Improved building of plugins	Clifford Wolf	2015-02-07	2	-3/+36
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*	Added "make uninstall"	Clifford Wolf	2015-02-07	1	-0/+4
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*	Added cell->known(), cell->input(portname), cell->output(portname)	Clifford Wolf	2015-02-07	2	-0/+39
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*	Added "select -read"	Clifford Wolf	2015-02-06	1	-5/+39
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*	Auto-detect TCL version	Clifford Wolf	2015-02-05	2	-2/+2
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*	Added onehot attribute	Clifford Wolf	2015-02-04	3	-0/+19
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*	Fixed opt_clean performance bug	Clifford Wolf	2015-02-04	1	-26/+26
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*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04	1	-6/+6
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*	Using design->selected_modules() in opt_*	Clifford Wolf	2015-02-03	5	-36/+20
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