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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-08 18:56:06 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-08 18:56:06 +0100 |
| commit | 09ee65a050ffc8fe1a208140cce32a6a5f15c4ab (patch) | |
| tree | a56b68832dfb8d6684a50ecec31b99770df5547f | |
| parent | 0fcc8c14674aecf6cf327740e6081bf722d806f6 (diff) | |
| download | yosys-09ee65a050ffc8fe1a208140cce32a6a5f15c4ab.tar.gz yosys-09ee65a050ffc8fe1a208140cce32a6a5f15c4ab.tar.bz2 yosys-09ee65a050ffc8fe1a208140cce32a6a5f15c4ab.zip | |
Added eval_select_args() and eval_select_op()
| -rw-r--r-- | kernel/register.h | 2 | ||||
| -rw-r--r-- | passes/cmds/select.cc | 31 |
2 files changed, 29 insertions, 4 deletions
diff --git a/kernel/register.h b/kernel/register.h index 5214dd9a3..9b247172e 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -100,6 +100,8 @@ struct Backend : Pass // implemented in passes/cmds/select.cc extern void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design); +extern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design); +extern void eval_select_op(vector<RTLIL::Selection> &work, string &op, RTLIL::Design *design); extern std::map<std::string, Pass*> pass_register; extern std::map<std::string, Frontend*> frontend_register; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 187db2a8b..f8cfa9ced 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -801,7 +801,7 @@ PRIVATE_NAMESPACE_END YOSYS_NAMESPACE_BEGIN // used in kernel/register.cc and maybe other locations, extern decl. in register.h -void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design) +void handle_extra_select_args(Pass *pass, vector<string> args, size_t argidx, size_t args_size, RTLIL::Design *design) { work_stack.clear(); for (; argidx < args_size; argidx++) { @@ -817,10 +817,33 @@ void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t select_op_union(design, work_stack.front(), work_stack.back()); work_stack.pop_back(); } - if (work_stack.size() > 0) - design->selection_stack.push_back(work_stack.back()); - else + if (work_stack.empty()) design->selection_stack.push_back(RTLIL::Selection(false)); + else + design->selection_stack.push_back(work_stack.back()); +} + +// extern decl. in register.h +RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design) +{ + work_stack.clear(); + for (auto &arg : args) + select_stmt(design, arg); + while (work_stack.size() > 1) { + select_op_union(design, work_stack.front(), work_stack.back()); + work_stack.pop_back(); + } + if (work_stack.empty()) + return RTLIL::Selection(false); + return work_stack.back(); +} + +// extern decl. in register.h +void eval_select_op(vector<RTLIL::Selection> &work, string &op, RTLIL::Design *design) +{ + work_stack.swap(work); + select_stmt(design, op); + work_stack.swap(work); } YOSYS_NAMESPACE_END |