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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-08 00:01:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-08 00:01:51 +0100 |
| commit | 05d4223fb675ee063ded20cf24eb922c4570634a (patch) | |
| tree | 482e8b06c23e13bf9719cd9b3748ad1991723579 | |
| parent | 0da320f151a343fc89f1fc94689f5921ed8fe4ea (diff) | |
| download | yosys-05d4223fb675ee063ded20cf24eb922c4570634a.tar.gz yosys-05d4223fb675ee063ded20cf24eb922c4570634a.tar.bz2 yosys-05d4223fb675ee063ded20cf24eb922c4570634a.zip | |
Added SigSpec::has_const()
| -rw-r--r-- | kernel/rtlil.cc | 12 | ||||
| -rw-r--r-- | kernel/rtlil.h | 1 |
2 files changed, 13 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b1e2c0e8e..776625b9c 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1078,6 +1078,7 @@ void RTLIL::Module::check() for (auto &it : connections_) { log_assert(it.first.size() == it.second.size()); + log_assert(!it.first.has_const()); it.first.check(); it.second.check(); } @@ -2968,6 +2969,17 @@ bool RTLIL::SigSpec::is_fully_undef() const return true; } +bool RTLIL::SigSpec::has_const() const +{ + cover("kernel.rtlil.sigspec.has_const"); + + pack(); + for (auto it = chunks_.begin(); it != chunks_.end(); it++) + if (it->width > 0 && it->wire == NULL) + return true; + return false; +} + bool RTLIL::SigSpec::has_marked_bits() const { cover("kernel.rtlil.sigspec.has_marked_bits"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 985bffe5e..dd40e2fba 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -672,6 +672,7 @@ public: bool is_fully_const() const; bool is_fully_def() const; bool is_fully_undef() const; + bool has_const() const; bool has_marked_bits() const; bool as_bool() const; |