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| * | | cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.whitequark2020-06-113-40/+62
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* | | Merge pull request #2152 from whitequark/cxxrtl-always-inlinewhitequark2020-06-131-4/+108
|\ \ \ | |_|/ |/| | cxxrtl: always inline internal cells and slice/concat operations
| * | cxxrtl: always inline internal cells and slice/concat operations.whitequark2020-06-131-4/+108
|/ / | | | | | | | | | | This can result in massive reduction in runtime, up to 50% depending on workload. Currently people are using `-mllvm -inline-threshold=` as a workaround (with clang++), but this solution is more portable.
* | Merge pull request #2150 from whitequark/cxxrtl-elide-pmuxwhitequark2020-06-121-30/+16
|\ \ | | | | | | cxxrtl: elide $pmux cells
| * | cxxrtl: elide $pmux cells.whitequark2020-06-121-30/+16
|/ / | | | | | | | | On Minerva, this improves runtime by around 10%, mostly by ensuring that the logic driving FFs is packed into edge conditionals.
* | Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputswhitequark2020-06-121-20/+24
|\ \ | | | | | | cxxrtl: unbuffer output wires of toplevel module
| * | cxxrtl: annotate port direction as comments.whitequark2020-06-121-1/+8
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| * | cxxrtl: unbuffer output wires of toplevel module.whitequark2020-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without unbuffering output wires of, at least, toplevel modules, it is not possible to have most designs that rely on IO via toplevel ports (as opposed to using exclusively blackboxes) converge within one delta cycle. That seriously impairs the performance of CXXRTL. This commit avoids unbuffering outputs of all modules solely so that in future, CXXRTL could gain fully separate compilation, and not for any present technical reason.
| * | cxxrtl: simplify unbuffering of input wires.whitequark2020-06-121-20/+17
| |/ | | | | | | This also fixes an edge case with (*keep*) input ports.
* / intel_alm: fix DFFE matchingDan Ravensloft2020-06-113-5/+5
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* Merge pull request #2141 from whitequark/cxxrtl-cxx11whitequark2020-06-103-8/+10
|\ | | | | cxxrtl: various compiler compatibility fixes
| * cxxrtl: restore C++11 compatibility.whitequark2020-06-101-1/+2
| | | | | | | | This is necessary to be able to build CXXRTL models via yosys-config.
| * cxxrtl: fix a few gcc warnings.whitequark2020-06-101-5/+6
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| * Fix formatting. NFC.whitequark2020-06-101-2/+2
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* | Merge pull request #2140 from whitequark/cxxrtl-aliaseswhitequark2020-06-104-9/+50
|\ \ | |/ |/| cxxrtl: disambiguate values/wires and their aliases in debug info
| * cxxrtl: disambiguate values/wires and their aliases in debug info.whitequark2020-06-104-9/+50
|/ | | | | | | With this change, it is easier to see which signals carry state (only wire<>s appear as `reg` in VCD files) and to construct a minimal checkpoint (CXXRTL_WIRE debug items represent the canonical smallest set of state required to fully reconstruct the simulation).
* Merge pull request #2134 from whitequark/cxxrtl-opt-debugwhitequark2020-06-101-52/+105
|\ | | | | cxxrtl: introduce -Og optimization level
| * cxxrtl: allow unbuffering without localizing.whitequark2020-06-091-40/+74
| | | | | | | | | | | | | | Although logically two separate steps, these were treated as one for historic reasons. Splitting the two makes it possible to have designs that are only 2× slower than fastest possible (and are without extra delta cycles) that allow probing all public wires.
| * cxxrtl: order -On levels as localize, elide instead of the reverse.whitequark2020-06-091-8/+8
| | | | | | | | | | | | | | | | | | | | | | Historically, elision was implemented before localization, so levels with elision are lower than corresponding levels with localization. This is unfortunate for two reasons: 1. Elision is a logical subset of localization, since it equals to not giving a name to a temporary. 2. "Localize" currently actually means "unbuffer and localize", and it would be useful to split those steps (at least for public wires) for improved design visibility.
| * cxxrtl: factor out -noproc/-noflatten from -O.whitequark2020-06-091-17/+36
| | | | | | | | | | | | | | | | Although these options can be thought of as optimizations, they are essentially orthogonal to the core of -O, which is managing signal buffering and scope. Going from -O4 to -O2 means going from limited to complete design visibility, yet in both cases proc and flatten are desirable.
* | Merge pull request #2131 from YosysHQ/claire/preserveffsclairexen2020-06-106-33/+50
|\ \ | | | | | | Do not optimize away FFs in "prep" and Verific front-end
| * | Fix tests/opt/opt_rmdffClaire Wolf2020-06-092-22/+29
| | | | | | | | | | | | | | | | | | This only passed before because "prep" was also running opt_rmdff Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Drive-by modernization in sat.ccClaire Wolf2020-06-091-4/+4
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-093-7/+17
| |/ | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #2139 from YosysHQ/verific_missing_memoryclairexen2020-06-101-2/+7
|\ \ | | | | | | verific - detect missing memory to prevent crash.
| * | verific - detect missing memory to prevent crash.Miodrag Milanovic2020-06-101-2/+7
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* | Merge pull request #2112 from YosysHQ/claire/fix2040clairexen2020-06-092-0/+58
|\ \ | |/ |/| Add latch detection for use_case_method in part-select write
| * Add latch detection for use_case_method in part-select write, fixes #2040Claire Wolf2020-06-042-0/+58
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #2128 from whitequark/flatten-processeswhitequark2020-06-093-10/+20
|\ \ | | | | | | flatten: accept processes
| * | flatten: accept processes.whitequark2020-06-091-8/+8
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| * | RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.whitequark2020-06-092-2/+12
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* | | Merge pull request #2130 from whitequark/cxxrtl-fix-split_bywhitequark2020-06-092-14/+16
|\ \ \ | |/ / |/| | cxxrtl: fix two buggy split_by functions
| * | cxxrtl: fix two buggy split_by functions.whitequark2020-06-092-14/+16
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* | Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-opswhitequark2020-06-092-64/+35
|\ \ | | | | | | cxxrtl: ignore cell input signedness when it is irrelevant
| * | cxxrtl: ignore cell input signedness when it is irrelevant.whitequark2020-06-092-64/+35
| | | | | | | | | | | | | | | | | | | | | | | | Before this commit, Verilog expressions like `x && 1` would result in references to `logic_and_us` in generated CXXRTL code, which would not compile. After this commit, since cells like that actually behave the same regardless of signedness attributes, the signedness is ignored, which also reduces the template instantiation pressure.
* | | Merge pull request #2125 from whitequark/cxxrtl-fix-namespacewhitequark2020-06-091-2/+2
|\ \ \ | |/ / |/| | cxxrtl: add missing namespace
| * | cxxrtl: add missing namespace.whitequark2020-06-091-2/+2
|/ / | | | | | | Fixes #2124.
* | Merge pull request #2107 from whitequark/flatten-hdlnamewhitequark2020-06-096-11/+54
|\ \ | | | | | | flatten: preserve original object names
| * | cxxrtl: fix format of hdlnames.whitequark2020-06-081-1/+1
| | | | | | | | | | | | | | | The CXXRTL code that handled the `hdlname` attribute implemented outdated semantics.
| * | flatten: preserve original object names via hdlname attribute.whitequark2020-06-085-6/+45
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| * | flatten: only prepend $flatten once per wire.whitequark2020-06-081-2/+6
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| * | RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.whitequark2020-06-081-2/+2
|/ / | | | | | | | | The only difference in behavior is that this removes the attribute when the pool becomes empty.
* | Merge pull request #2120 from whitequark/flatten-hygienewhitequark2020-06-081-155/+116
|\ \ | | | | | | flatten: make hygienic
| * | flatten: make hygienic.whitequark2020-06-081-155/+116
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, `flatten` matched the template objects with the newly created objects solely by their name. Because of this, it could be confused by code such as: module bar(); $dff a(); endmodule module foo(); bar b(); $dff \b.a (); endmodule After this commit, `flatten` avoids every possible case of name collision. Fixes #2106.
* | Merge pull request #2121 from whitequark/cxxrtl-debug-aliaseswhitequark2020-06-085-25/+120
|\ \ | | | | | | cxxrtl: improve design visibility
| * | cxxrtl: don't check immutable values for changes in VCD writer.whitequark2020-06-081-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the VCD writer such that for all signals that have `debug_item.type == VALUE && debug_item.next == nullptr`, it would only sample the value once. Commit f2d7a187 added more debug information by including constant wires, and decreased the performance of VCD writer proportionally because the constant wires were still repeatedly sampled; this commit eliminates the performance hit.
| * | cxxrtl: emit debug information for constant wires.whitequark2020-06-083-17/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | Constant wires can represent a significant chunk of the design in generic designs or after optimization. Emitting them in VCD files significantly improves usability because gtkwave removes all traces that are not present in the VCD file after reload, and iterative development suffers if switching a varying signal to a constant disrupts the workflow.
| * | cxxrtl: track aliases in VCD writer.whitequark2020-06-081-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the VCD writer such that for all signals that share `debug_item.curr`, it would only emit a single VCD identifier, and sample the value once. Commit 9b39c6f7 added redundancy to debug information by including alias wires, and increased the size of VCD files proportionally; this commit eliminates the redundancy from VCD files so that their size is the same as before.
| * | cxxrtl: emit debug information for alias wires.whitequark2020-06-081-3/+55
| | | | | | | | | | | | | | | | | | | | | Alias wires can represent a significant chunk of the design in highly hierarchical designs; in Minerva SRAM, there are 273 member wires and 527 alias wires. Showing them in every hierarchy level significantly improves usability.
| * | cxxrtl: add missing installs of include files.whitequark2020-06-081-0/+5
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