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authorClaire Wolf <claire@symbioticeda.com>2020-06-09 21:49:43 +0200
committerClaire Wolf <claire@symbioticeda.com>2020-06-09 22:48:26 +0200
commit0bd70e8222c9a95352dd880df1099e3185793004 (patch)
tree7a75ff5e3c045a26c1675d9ccecf2e30e01acfed
parent3c7122c3788a05d90423f22ec03f97c39da2da0b (diff)
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Drive-by modernization in sat.cc
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
-rw-r--r--passes/sat/sat.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 6acdbc800..e2fe5b846 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -256,13 +256,13 @@ struct SatHelper
{
RTLIL::SigSpec big_lhs, big_rhs;
- for (auto &it : module->wires_)
+ for (auto wire : module->wires())
{
- if (it.second->attributes.count(ID::init) == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
- RTLIL::SigSpec lhs = sigmap(it.second);
- RTLIL::SigSpec rhs = it.second->attributes.at(ID::init);
+ RTLIL::SigSpec lhs = sigmap(wire);
+ RTLIL::SigSpec rhs = wire->attributes.at(ID::init);
log_assert(lhs.size() == rhs.size());
RTLIL::SigSpec removed_bits;