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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-10 11:27:44 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-10 11:27:44 +0200 |
| commit | d6bec3ba1c81ebd123a58231f790564aa99444ff (patch) | |
| tree | b9974c0f5b93951ebd6f245d30a713ef09741b22 | |
| parent | 5c426d2bff07825042b0fa0449805ea9cb8b9f58 (diff) | |
| download | yosys-d6bec3ba1c81ebd123a58231f790564aa99444ff.tar.gz yosys-d6bec3ba1c81ebd123a58231f790564aa99444ff.tar.bz2 yosys-d6bec3ba1c81ebd123a58231f790564aa99444ff.zip | |
verific - detect missing memory to prevent crash.
| -rw-r--r-- | frontends/verific/verific.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index cb0368fd5..65e71876a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1262,7 +1262,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == OPER_READ_PORT) { - RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name())); + RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()), nullptr); + if (!memory) + log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name()); + int numchunks = int(inst->OutputSize()) / memory->width; int chunksbits = ceil_log2(numchunks); @@ -1289,7 +1292,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT) { - RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name())); + RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()), nullptr); + if (!memory) + log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name()); int numchunks = int(inst->Input2Size()) / memory->width; int chunksbits = ceil_log2(numchunks); |