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| * Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
| * greenpak4: Added support for inferred input/output inverters on latchesAndrew Zonenberg2016-12-101-4/+17
| * greenpak4: Can now techmap inferred D latches (without set/reset or output in...Andrew Zonenberg2016-12-103-0/+17
| * greenpak4: Inverted D latch cells now have nQ instead of Q as output port nam...Andrew Zonenberg2016-12-101-15/+15
| * Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
| * Initial implementation of techlib support for GreenPAK latches. Instantiation...Andrew Zonenberg2016-12-052-0/+120
| * Updated help text for synth_greenpak4Andrew Zonenberg2016-12-051-0/+2
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* Added $assert/$assume support to AIGER back-endClifford Wolf2016-12-033-13/+54
* Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aigClifford Wolf2016-12-031-2/+15
* Updated ABV to hg rev 8b555d9e67cfClifford Wolf2016-12-011-1/+1
* Added examples/aiger/Clifford Wolf2016-12-014-0/+53
* Added "yosys-smtbmc --aig"Clifford Wolf2016-12-011-6/+127
* Added support for partially initialized regs to smt2 back-endClifford Wolf2016-12-011-3/+15
* Added "write_aiger -zinit -symbols -vmap"Clifford Wolf2016-12-011-30/+139
* Added "write_aiger" commandClifford Wolf2016-11-302-0/+398
* Added "design -reset-vlog"Clifford Wolf2016-11-301-7/+32
* Improved equiv_purge log outputClifford Wolf2016-11-291-1/+1
* Bugfix in smt2 back-end for pure checker modulesClifford Wolf2016-11-281-0/+4
* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
* Bugfix in "read_verilog -D NAME=VAL" handlingClifford Wolf2016-11-281-3/+3
* Removed shebang line from smtio.py, fixes #279Clifford Wolf2016-11-271-1/+0
* Added wire start_offset and upto handling BLIF back-endClifford Wolf2016-11-231-1/+1
* Added wire start_offset and upto handling to splitnets cmdClifford Wolf2016-11-231-2/+8
* Merge pull request #274 from oldtopman/lcursesClifford Wolf2016-11-221-0/+5
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| * Added optional flag for linking curses with readline.oldtopman2016-11-211-0/+5
* | Added "yosys-smtbmc --append"Clifford Wolf2016-11-221-2/+20
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* Merge pull request #272 from AlexDaniel/masterClifford Wolf2016-11-191-63/+64
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| * Keep lines under 80 charactersAleks-Daniel Jakimenko-Aleksejev2016-11-191-10/+11
| * Markdownify README even furtherAleks-Daniel Jakimenko-Aleksejev2016-11-191-60/+60
* | Improved ABC default scriptsClifford Wolf2016-11-191-17/+34
* | Merge pull request #271 from azidar/bugfix-assign-wmaskClifford Wolf2016-11-191-0/+1
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| * Bugfix: include assign to write-maskAdam Izraelevitz2016-11-181-0/+1
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* More progress in FIRRTL back-endClifford Wolf2016-11-183-4/+121
* Progress in FIRRTL back-endClifford Wolf2016-11-184-5/+55
* Added first draft of FIRRTL back-endClifford Wolf2016-11-172-0/+353
* Cleanups and fixed in write_verilog regarding reg initClifford Wolf2016-11-161-15/+61
* Added support for hierarchical defparamsClifford Wolf2016-11-155-17/+65
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-156-8/+23
* Merge pull request #268 from AlexDaniel/masterClifford Wolf2016-11-131-34/+27
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| * Markdownify READMEAleks-Daniel Jakimenko-Aleksejev2016-11-121-34/+27
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* Minor bugfix in submodClifford Wolf2016-11-091-0/+1
* Progress in examples/gowin/Clifford Wolf2016-11-085-21/+95
* Indenting fixes in gowin sim cell libClifford Wolf2016-11-081-20/+28
* Bugfix in "setundef" passClifford Wolf2016-11-081-2/+7
* Added examples/gowin/Clifford Wolf2016-11-076-0/+57
* Implemented "scc -set_attr"Clifford Wolf2016-11-061-22/+32
* Bugfix in "scc" commandClifford Wolf2016-11-061-9/+11
* Fixed anonymous genblock object namesClifford Wolf2016-11-041-1/+1
* Added hex constant support to write_verilogClifford Wolf2016-11-032-5/+63
* We are now in 0.7+ developmentClifford Wolf2016-11-031-1/+1
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