iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Helper: SigSpec::operator[] to accept negative indices	Eddie Hung	2019-07-31	1	-2/+2
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*	Fix spacing	Eddie Hung	2019-07-26	1	-3/+3
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*	Update test_autotb doc to reflect default value of zero	Eddie Hung	2019-07-26	1	-1/+3
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*	Add doc for "test_autotb -seed" option	Eddie Hung	2019-07-26	1	-0/+3
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*	Pop the CO bit from O	Eddie Hung	2019-07-26	1	-1/+3
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*	Allow adders/accumulators with 33 bits using CO output	Eddie Hung	2019-07-26	1	-3/+8
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*	Add copyright header, comment on cascade	Eddie Hung	2019-07-24	1	-4/+34
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*	Eliminate warnings by sizing O correctly	Eddie Hung	2019-07-23	1	-1/+5
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*	Typo for Y_WIDTH	Eddie Hung	2019-07-23	1	-1/+1
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*	Fix muxAB logic	Eddie Hung	2019-07-23	1	-3/+2
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*	Remove debug print	Eddie Hung	2019-07-23	1	-1/+1
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*	Simplify and fix for MACs	Eddie Hung	2019-07-23	2	-56/+38
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*	Fix typo	Eddie Hung	2019-07-23	1	-13/+21
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*	Fix spacing	Eddie Hung	2019-07-22	1	-2/+2
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*	Remove debug	Eddie Hung	2019-07-22	1	-1/+0
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*	Pack hi and lo registers separately	Eddie Hung	2019-07-22	2	-39/+70
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*	SigSpec::extract() to return as many bits as poss if out of bounds	Eddie Hung	2019-07-22	1	-1/+7
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*	Rename according to vendor doc TN1295	Eddie Hung	2019-07-22	3	-55/+56
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*	Pack Y register	Eddie Hung	2019-07-22	2	-22/+38
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*	opt and wreduce necessary for -dsp	Eddie Hung	2019-07-22	1	-2/+4
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*	Pack adders not just accumulators	Eddie Hung	2019-07-22	2	-16/+33
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*	Use minimum sized width wires	Eddie Hung	2019-07-22	1	-7/+13
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*	Restore old ffY behaviour	Eddie Hung	2019-07-19	1	-16/+5
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*	Cleanup	Eddie Hung	2019-07-19	1	-5/+5
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*	Indirection via $__soft_mul	Eddie Hung	2019-07-19	2	-9/+10
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*	Do not do sign extension in techmap; let packer do it	Eddie Hung	2019-07-19	1	-14/+5
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*	Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp	Eddie Hung	2019-07-19	3	-5/+29
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\| *	Add another test	Eddie Hung	2019-07-19	1	-1/+24
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\| *	Do not access beyond bounds	Eddie Hung	2019-07-19	1	-1/+1
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\| *	Add an SigSpec::at(offset, defval) convenience method	Eddie Hung	2019-07-19	1	-0/+1
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\| *	Wrap A and B in sigmap	Eddie Hung	2019-07-19	1	-2/+2
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\| *	Remove "top" from message	Eddie Hung	2019-07-19	1	-1/+1
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* \|	Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp	Eddie Hung	2019-07-19	2	-3/+121
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\| *	Also optimise MSB of $sub	Eddie Hung	2019-07-19	1	-3/+3
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\| *	Add one more test with trimming Y_WIDTH of $sub	Eddie Hung	2019-07-19	1	-11/+14
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\| *	Be more explicit	Eddie Hung	2019-07-19	1	-6/+29
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\| *	wreduce for $sub	Eddie Hung	2019-07-19	1	-0/+23
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\| *	Add tests for sub too	Eddie Hung	2019-07-19	1	-1/+48
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\| *	Add test	Eddie Hung	2019-07-19	1	-0/+22
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\| *	SigSpec::extract to take negative lengths	Eddie Hung	2019-07-19	1	-1/+1
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* \|	Do not $mul -> $__mul if A and B are less than maxwidth	Eddie Hung	2019-07-19	1	-1/+3
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* \|	Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold	Eddie Hung	2019-07-19	1	-1/+1
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* \|	Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too	Eddie Hung	2019-07-19	1	-28/+68
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* \|	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	Eddie Hung	2019-07-19	4	-35/+47
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* \|	Add support for ice40 signed multipliers	Eddie Hung	2019-07-19	1	-13/+8
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* \|	Merge branch 'xc7dsp' into ice40dsp	Eddie Hung	2019-07-19	1	-1/+1
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\| * \|	Fix typo in B	Eddie Hung	2019-07-19	1	-1/+1
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\| * \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-07-18	29	-228/+405
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* \| \|	Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp	Eddie Hung	2019-07-19	3	-7/+239
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\| * \| \|	ice40: Fix test_dsp_model.sh	David Shah	2019-07-19	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: David Shah <dave@ds0.me>