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This commit changes the VCD writer such that for all signals that
share `debug_item.curr`, it would only emit a single VCD identifier,
and sample the value once.
Commit 9b39c6f7 added redundancy to debug information by including
alias wires, and increased the size of VCD files proportionally; this
commit eliminates the redundancy from VCD files so that their size
is the same as before.
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Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
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Silence warning in select.cc and pass some more args by ref
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Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.
Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
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- Pass a string argument by reference
- Avoid multiple calls to IdString::str and IdString::c_str
- Avoid combining checks for size > 0 and first char (C strings are
null terminated, so foo[0] != '\0' implies that foo has positive
length)
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With GCC 9.3, at least, compiling select.cc spits out a warning about
an implausible bound being passed to strncmp. This comes from inlining
IdString::compare(): it turns out that passing std::string::npos as a
bound to strncmp triggers it.
This patch replaces the compare call with a memcmp with the same
effect. The repeated calls to IdString::c_str are slightly
inefficient, but I'll address that in a follow-up commit.
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Simplify a modport check in hierarchy.cc
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This code originally comes from commit 458a940. When an interface is
used via a modport, code in genrtlil.cc sets '\\interface_type' and
'\\interface_modport' properties on the wire.
In hierarchy.cc, we pick up the modport name and add it to a dict
called modports_used_in_submodule (that maps connection source to
modport name).
Before this patch, the modport name is retrieved as a strpool and then
iterated over in an arbitrary order, discarding all entries but the
last. In practice, the pool will always have 0 or 1 entries because
the string used to construct it is a valid identifier, so doesn't
contain any pipe symbols.
This patch changes the code to retrieve the modport name as just a
string. This will have the same effect in practice, but may be a bit
less confusing!
The code also gets moved down closer to where the result is used,
which might be a bit more efficient since we won't always get as far
as the check.
The patch also removes some commented-out code, which I think was
intended to add some typechecking at some point, but was never
implemented. Since this dates back to October 2018, I think it makes
more sense to just take it out.
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Split `flatten` from `techmap` and simplify it
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`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
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Remove redundant sigmaps.
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Flattening does not benefit from topologically sorting cells within
a module when processing them.
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Flatten is non-recursive and doesn't need to keep track of handled
cells.
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Flattening always does "non-recursive" mapping.
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The `celltypeMap` always maps `x` to `{x}`.
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The `design` and `map` designs are always the same when flattening.
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After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
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Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
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Support packed arrays in struct/union.
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fsm_extract: avoid calling log_signal to determine wire name
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log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
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cxxrtl: add a VCD writer using debug information
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To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
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This C API is fully featured.
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On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
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cxxrtl: add debug information to the C++ API, and add introspection via a new C API
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Compared to the C++ API, the C API currently has two limitations:
1. Memories cannot be updated in a race-free way.
2. Black boxes cannot be implemented in C.
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Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.
The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
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MacOS has even stricter stack limits in catalina.
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Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
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cxxrtl: fix implementation of $sshr cell
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Fixes #2111.
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btor backend: make not printing internal names default
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Implementation of SV structs.
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