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author | clairexen <claire@symbioticeda.com> | 2020-06-08 15:48:11 +0200 |
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committer | GitHub <noreply@github.com> | 2020-06-08 15:48:11 +0200 |
commit | 0f209378a8e7b11bfabe40c54d445fceac12c2cb (patch) | |
tree | 71591895cb6d7fe1d5349ab29e2a66ed4879145f | |
parent | fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd (diff) | |
parent | 7746bba69a781498a13157a9c544b34ced8ad0a8 (diff) | |
download | yosys-0f209378a8e7b11bfabe40c54d445fceac12c2cb.tar.gz yosys-0f209378a8e7b11bfabe40c54d445fceac12c2cb.tar.bz2 yosys-0f209378a8e7b11bfabe40c54d445fceac12c2cb.zip |
Merge pull request #2089 from rswarbrick/modports
Simplify a modport check in hierarchy.cc
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index f99d1509d..b4eb0f1dd 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -254,16 +254,6 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // some lists, so that the ports for sub-modules can be replaced further down: for (auto &conn : cell->connections()) { if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list - //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_type); - //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness) - //} - - // Find if the sub-module has set a modport for the current interface connection: - const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_modport); - std::string interface_modport = ""; - for (auto &d : interface_modport_pool) { - interface_modport = "\\" + d; - } if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute(ID::is_interface)) { // Check if the connected wire is a potential interface in the parent module std::string interface_name_str = conn.second.bits()[0].wire->name.str(); interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name @@ -297,9 +287,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check connections_to_remove.push_back(conn.first); interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name2); - // Add modports to a dict which will be passed to AstModule::derive - if (interface_modport != "") { - modports_used_in_submodule[conn.first] = interface_modport; + // Find if the sub-module has set a modport for the current + // interface connection. Add any modports to a dict which will + // be passed to AstModule::derive + string modport_name = mod->wire(conn.first)->get_string_attribute(ID::interface_modport); + if (!modport_name.empty()) { + modports_used_in_submodule[conn.first] = "\\" + modport_name; } } else not_found_interface = true; |