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| author | whitequark <whitequark@whitequark.org> | 2020-06-08 04:08:09 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-08 12:50:35 +0000 |
| commit | 8262997c4ea1cb6acafb5d8f29f1300da2746d5e (patch) | |
| tree | 2fdaf8610a09fcad049c4ccb102b691093e1e942 | |
| parent | fb3704c8964aac37b6745647cb6338d464ff38fb (diff) | |
| download | yosys-8262997c4ea1cb6acafb5d8f29f1300da2746d5e.tar.gz yosys-8262997c4ea1cb6acafb5d8f29f1300da2746d5e.tar.bz2 yosys-8262997c4ea1cb6acafb5d8f29f1300da2746d5e.zip | |
cxxrtl: fix typo in comment. NFC.
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index e2fd6b672..a43a23d04 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -359,10 +359,10 @@ struct FlowGraph { // // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not - // as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have a sync def, - // and this node would be an ordinary CONNECT node, with `\lhs` having a comb def. Because it isn't, - // a special node type is used, the right-hand side does not appear anywhere, and the left-hand - // side has a comb def. + // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have + // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def. + // Because it isn't, a special node type is used, the right-hand side does not appear anywhere, + // and the left-hand side has a comb def. for (auto conn : cell->connections()) if (cell->output(conn.first)) if (is_cxxrtl_sync_port(cell, conn.first)) { |