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* | | gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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* | Merge pull request #1507 from YosysHQ/clifford/verificfixesClifford Wolf2019-11-202-6/+9
|\ \ | | | | | | Some fixes in our Verific integration
| * | Correctly treat empty modules as blackboxes in VerificClifford Wolf2019-11-201-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Do not rename VHDL entities to "entity(impl)" when they are top modulesClifford Wolf2019-11-202-5/+8
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1927-89/+841
|\ \ | | | | | | Improvements for gowin support
| * | Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | | | | | | | | | | | | | | The hardware does not actually support it. In reality it is always initialised to its reset value.
| * | add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
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| * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1615-47/+913
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| * | | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-112-4/+15
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| * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1129-23010/+30701
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| * | | | fix wide lutsPepijn de Vos2019-11-062-19/+22
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| * | | | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
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| * | | | add IOBUFPepijn de Vos2019-10-282-1/+10
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| * | | | add tristate buffer and testPepijn de Vos2019-10-283-2/+21
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| * | | | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
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| * | | | actually run the gowin testsPepijn de Vos2019-10-281-0/+1
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| * | | | More formattingPepijn de Vos2019-10-281-55/+49
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| * | | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
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| * | | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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| * | | | add wide lutsPepijn de Vos2019-10-283-36/+119
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| * | | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
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| * | | | ALU sim tweaksPepijn de Vos2019-10-242-13/+13
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| * | | | Add some testsPepijn de Vos2019-10-2110-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram
| * | | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
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| * | | | add negedge DFFPepijn de Vos2019-10-212-15/+139
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| * | | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
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| * | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-21275-2678/+32872
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| * | | | | remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
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| * | | | | Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
| * | | | | fix BRAM width and initPepijn de Vos2019-09-062-12/+28
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| * | | | | add more DFF to sim libPepijn de Vos2019-09-062-6/+111
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| * | | | | WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
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| * | | | | support bram initialisationPepijn de Vos2019-09-055-3/+25
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| * | | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
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| * | | | | add MUX supportPepijn de Vos2019-09-053-0/+17
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| * | | | | set undriven pads to zeroPepijn de Vos2019-09-042-2/+3
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| * | | | | fix tcl scriptPepijn de Vos2019-09-041-2/+1
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| * | | | | add broken TCL run scriptPepijn de Vos2019-09-042-0/+18
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| * | | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| | * | | | | Updating gowinDiego H2019-09-022-2/+2
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| * | | | | | Add demonstration of breakagePepijn de Vos2019-09-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unused outputs lead to undriven buffers, which lead to syntax errors.
| * | | | | | Update example for GW1NR-9Pepijn de Vos2019-09-044-47/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the Trenz TEC0117 on Gowin IDE 1.8.4
| * | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosysPepijn de Vos2019-09-043-5/+6
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| * | | | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
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* | | | | | | | Fix #1462, #1480.Marcin Kościelnicki2019-11-194-9/+40
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* | | | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| |_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
* | | | | | | Merge pull request #1497 from YosysHQ/mwk/extract-fa-fixClifford Wolf2019-11-182-4/+21
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Fix #1496.
| * | | | | | | Fix #1496.Marcin Kościelnicki2019-11-182-4/+21
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* | | | | | | | Merge pull request #1494 from whitequark/write_verilog-extmemwhitequark2019-11-181-10/+80
|\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | | write_verilog: add -extmem option, to write split memory init files
| * | | | | | | write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.
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