| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added "make -j{N}" support to "make test" | Clifford Wolf | 2014-07-30 | 7 | -22/+39 |
| * | Improvements in test_cell | Clifford Wolf | 2014-07-30 | 1 | -35/+89 |
| * | New techmap default rules for $shr $sshr $shl $sshl | Clifford Wolf | 2014-07-30 | 1 | -282/+62 |
| * | Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models | Clifford Wolf | 2014-07-30 | 1 | -36/+39 |
| * | Added native support for shift operations to ezSAT | Clifford Wolf | 2014-07-30 | 2 | -1/+95 |
| * | Added "log_dump_val_worker(char *v)" | Clifford Wolf | 2014-07-30 | 1 | -0/+1 |
| * | Added CodingStyle document | Clifford Wolf | 2014-07-30 | 1 | -0/+43 |
| * | Added "kernel/yosys.h" and "kernel/yosys.cc" | Clifford Wolf | 2014-07-30 | 8 | -61/+133 |
| * | Added "test_cell" command | Clifford Wolf | 2014-07-29 | 3 | -1/+186 |
| * | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ | Clifford Wolf | 2014-07-29 | 5 | -10/+12 |
| * | Fixed Verilog pre-processor for files with no trailing newline | Clifford Wolf | 2014-07-29 | 1 | -1/+1 |
| * | Bugfix in simlib.v for iverilog | Clifford Wolf | 2014-07-29 | 1 | -5/+6 |
| * | Allow "hierarchy -generate" for $__ cells | Clifford Wolf | 2014-07-29 | 1 | -1/+3 |
| * | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 | 4 | -10/+29 |
| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 12 | -40/+214 |
| * | Removed left over debug code | Clifford Wolf | 2014-07-28 | 2 | -2/+0 |
| * | Fixed part selects of parameters | Clifford Wolf | 2014-07-28 | 2 | -7/+31 |
| * | Set results of out-of-bounds static bit/part select to undef | Clifford Wolf | 2014-07-28 | 1 | -5/+31 |
| * | Fixed RTLIL code generator for part select of parameter | Clifford Wolf | 2014-07-28 | 1 | -2/+2 |
| * | Fixed width detection for part selects | Clifford Wolf | 2014-07-28 | 1 | -2/+2 |
| * | Added support for "upto" wires to Verilog front- and back-end | Clifford Wolf | 2014-07-28 | 6 | -22/+96 |
| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 6 | -2/+13 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 52 | -251/+236 |
| * | Added std::initializer_list<> constructor to SigSpec | Clifford Wolf | 2014-07-28 | 2 | -0/+15 |
| * | Added cover() to all SigSpec constructors | Clifford Wolf | 2014-07-28 | 1 | -0/+22 |
| * | Fixed signdness detection of expressions with bit- and part-selects | Clifford Wolf | 2014-07-28 | 1 | -0/+1 |
| * | Improvements in tests/vloghtb | Clifford Wolf | 2014-07-28 | 2 | -11/+17 |
| * | Added techmap -extern | Clifford Wolf | 2014-07-27 | 3 | -17/+92 |
| * | Added proper Design->addModule interface | Clifford Wolf | 2014-07-27 | 3 | -4/+43 |
| * | Added topological sorting to techmap | Clifford Wolf | 2014-07-27 | 2 | -21/+54 |
| * | Added SigPool::check(bit) | Clifford Wolf | 2014-07-27 | 2 | -2/+7 |
| * | Small improvements in PerformanceTimer API | Clifford Wolf | 2014-07-27 | 1 | -6/+7 |
| * | Fixed bug in opt_clean | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Improved performance of opt_const on large modules | Clifford Wolf | 2014-07-27 | 2 | -29/+157 |
| * | Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs | Clifford Wolf | 2014-07-27 | 1 | -9/+26 |
| * | Added RTLIL::SigSpecConstIterator | Clifford Wolf | 2014-07-27 | 1 | -0/+18 |
| * | Fixed a bug in opt_clean and some RTLIL API usage cleanups | Clifford Wolf | 2014-07-27 | 2 | -13/+14 |
| * | Added log_cmd_error_expection | Clifford Wolf | 2014-07-27 | 4 | -8/+7 |
| * | Fixed verific bindings for new RTLIL api | Clifford Wolf | 2014-07-27 | 2 | -55/+42 |
| * | Fixed ilang parser for new RTLIL API | Clifford Wolf | 2014-07-27 | 1 | -10/+10 |
| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 10 | -87/+85 |
| * | Added RTLIL::Module::wire(id) and cell(id) lookup functions | Clifford Wolf | 2014-07-27 | 2 | -2/+20 |
| * | Added RTLIL::Design::modules() | Clifford Wolf | 2014-07-27 | 1 | -0/+3 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 73 | -223/+223 |
| * | Added conversion from ObjRange to std::vector and std::set | Clifford Wolf | 2014-07-27 | 1 | -0/+15 |
| * | Added RTLIL::ObjIterator and RTLIL::ObjRange | Clifford Wolf | 2014-07-27 | 2 | -7/+111 |
| * | Using std::move() in SigSpec move constructor | Clifford Wolf | 2014-07-27 | 1 | -4/+4 |
| * | Added RTLIL::SigSpec move constructor and move assignment operator | Clifford Wolf | 2014-07-27 | 1 | -0/+15 |
| * | Mostly cosmetic changes to rtlil.h | Clifford Wolf | 2014-07-27 | 1 | -17/+57 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 61 | -152/+152 |
