| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | fix bug: pass by reference | tklam | 2018-09-26 | 1 | -1/+1 | |
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| | * | | | | | | Fix issue #639 | TK Lam | 2018-09-26 | 1 | -0/+58 | |
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| * | | | | | | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | Fix issue #630 | |||||
| | * | | | | | | | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (as well as a non critical minor code optimization) | |||||
| | * | | | | | | | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 226 | -1397/+5434 | |
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| | * | | | | | | | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule | |||||
| * | | | | | | | | | We have 2018 now | Clifford Wolf | 2018-10-16 | 2 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | After release is before release | Clifford Wolf | 2018-10-16 | 2 | -1/+9 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Merge branch 'yosys-0.8-rc' | Clifford Wolf | 2018-10-16 | 2 | -141/+1201 | |
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| | * | | | | | | | | Yosys 0.8 | Clifford Wolf | 2018-10-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | | Update command reference manual | Clifford Wolf | 2018-10-16 | 1 | -140/+1200 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Improve Verific importer blackbox handling | Clifford Wolf | 2018-10-07 | 1 | -2/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Merge pull request #651 from ARandomOWL/stdcells_fix | Clifford Wolf | 2018-10-05 | 1 | -1/+1 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Fix IdString M in setup_stdcells() | |||||
| | * | | | | | | | | | Fix IdString M in setup_stdcells() | Adrian Wheeldon | 2018-10-04 | 1 | -1/+1 | |
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| * | | | | | | | | | Add "write_edif -attrprop" | Clifford Wolf | 2018-10-05 | 1 | -11/+28 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | Merge pull request #654 from mithro/patch-1 | Clifford Wolf | 2018-10-05 | 1 | -1/+1 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Fix misspelling in issue_template.md | |||||
| | * | | | | | | | | | Fix misspelling in issue_template.md | Tim Ansell | 2018-10-04 | 1 | -1/+1 | |
| | | |_|_|_|_|/ / / | |/| | | | | | | | | | | | | | | | | It's been bugging me :-P | |||||
| * / | | | | | | | | Fix compiler warning in verific.cc | Clifford Wolf | 2018-10-05 | 1 | -0/+2 | |
| |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Add inout ports to cells_xtra.v | Clifford Wolf | 2018-10-04 | 2 | -2/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Merge pull request #650 from mithro/patch-1 | Clifford Wolf | 2018-10-04 | 1 | -0/+1 | |
| |\ \ \ \ \ \ \ \ | |_|_|_|_|/ / / |/| | | | | | | | xilinx: Adding missing inout IO port to IOBUF | |||||
| | * | | | | | | | xilinx: Adding missing inout IO port to IOBUF | Tim Ansell | 2018-10-03 | 1 | -0/+1 | |
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| * | | | | | | | Merge pull request #645 from daveshah1/ecp5_dram_fix | Clifford Wolf | 2018-10-02 | 1 | -0/+1 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | ecp5: Don't map ROMs to DRAM | |||||
| | * | | | | | | | ecp5: Don't map ROMs to DRAM | David Shah | 2018-10-01 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | | | | Merge pull request #646 from tomverbeure/issue594 | Clifford Wolf | 2018-10-02 | 1 | -1/+2 | |
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | Fix for issue 594. | |||||
| | * | | | | | | | | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 | |
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| * | | | | | | / | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 | |
| | |_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-09-30 | 1 | -1/+1 | |
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| | * | | | | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-09-28 | 1 | -4/+4 | |
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| | * | | | | | Update to v2 YosysVS template | Clifford Wolf | 2018-09-28 | 1 | -4/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 3 | -6/+49 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵ | Clifford Wolf | 2018-09-23 | 1 | -3/+9 | |
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc | Clifford Wolf | 2018-09-23 | 1 | -11/+11 | |
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| | * | | | | | added prefix to FDirection constants, fixing windows build | Miodrag Milanovic | 2018-09-21 | 1 | -11/+11 | |
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| * | | | | | | Update CHANGELOG | Clifford Wolf | 2018-09-23 | 1 | -2/+35 | |
| |/ / / / / | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Update CHANGLELOG | Clifford Wolf | 2018-09-21 | 1 | -5/+27 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Update Changelog | Clifford Wolf | 2018-09-21 | 1 | -1/+54 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Merge pull request #633 from mmicko/master | Clifford Wolf | 2018-09-19 | 3 | -1/+14 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Fix Cygwin build and document needed packages | |||||
| | * | | | | | Fix Cygwin build and document needed packages | Miodrag Milanovic | 2018-09-19 | 3 | -1/+14 | |
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| * | | | | | Merge pull request #631 from acw1251/master | Clifford Wolf | 2018-09-19 | 2 | -5/+5 | |
| |\ \ \ \ \ | |/ / / / |/| | | | | Fixed typo in "verilog_write" help message | |||||
| | * | | | | Fixed typo in "verilog_write" help message | acw1251 | 2018-09-18 | 2 | -5/+5 | |
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| * | | | | Merge pull request #625 from aman-goel/master | Clifford Wolf | 2018-09-14 | 1 | -1/+7 | |
| |\ \ \ \ | | |_|/ | |/| | | Minor revision to -expose in setundef pass | |||||
| | * | | | Minor revision to -expose in setundef pass | Aman Goel | 2018-09-10 | 1 | -1/+7 | |
| | | | | | | | | | | | | | | | | | Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort. | |||||
| * | | | | Merge pull request #627 from acw1251/master | Clifford Wolf | 2018-09-14 | 1 | -1/+1 | |
| |\ \ \ \ | | | | | | | | | | | Fixed minor typo in "sim" help message | |||||
| | * | | | | Fixed minor typo in "sim" help message | acw1251 | 2018-09-12 | 1 | -1/+1 | |
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| * | / / | Add iCE40 SB_SPRAM256KA simulation model | Clifford Wolf | 2018-09-10 | 1 | -9/+30 | |
| | |/ / |/| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add $lut support to Verilog back-end | Clifford Wolf | 2018-09-06 | 1 | -0/+13 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "verific -L <int>" option | Clifford Wolf | 2018-09-04 | 3 | -2/+16 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "make ystests" | Clifford Wolf | 2018-08-30 | 3 | -0/+10 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add GCC to osx deps (#620) | Miodrag Milanović | 2018-08-28 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | * Add GCC to osx deps * Force gcc-7 install | |||||
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index : iCE40/yosys | |
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