| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | Adds missing "end" and eol to module. | Robert Baruch | 2020-11-22 | 1 | -1/+1 | |
| | * | | | | Update to Values #2 | Robert Baruch | 2020-11-22 | 1 | -1/+1 | |
| | * | | | | Update to Values section | Robert Baruch | 2020-11-22 | 1 | -2/+2 | |
| | * | | | | Adds appendix on RTLIL text format | Robert Baruch | 2020-11-22 | 3 | -0/+260 | |
| * | | | | | Bump required Verific version | Miodrag Milanovic | 2020-12-02 | 1 | -1/+1 | |
| * | | | | | Bump version | Yosys Bot | 2020-12-02 | 1 | -1/+1 | |
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| * | | | | Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines | Claire Xen | 2020-12-01 | 2 | -1/+3 | |
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| | * | | | Fix SYNTHESIS always being defined in Verilog frontend | georgerennie | 2020-12-01 | 2 | -1/+3 | |
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| * | | | Merge pull request #2460 from pepijndevos/simple-gowin | Miodrag Milanović | 2020-12-01 | 1 | -3/+32 | |
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| | * | | add -noalu and -json option for apicula | Pepijn de Vos | 2020-11-30 | 1 | -3/+32 | |
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| * | | Bump version | Yosys Bot | 2020-11-26 | 1 | -1/+1 | |
| * | | Merge pull request #2452 from whitequark/rtlil-remove-dot-identifiers | whitequark | 2020-11-25 | 1 | -1/+0 | |
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| | * | | rtlil: remove dotted identifiers. | whitequark | 2020-11-25 | 1 | -1/+0 | |
| * | | | Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments | Miodrag Milanović | 2020-11-25 | 1 | -6/+26 | |
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| | * | | | Add verilog backend option for simple_lhs | Miodrag Milanovic | 2020-11-25 | 1 | -6/+22 | |
| | * | | | generate only simple assignments in verilog backend | Miodrag Milanovic | 2020-11-25 | 1 | -5/+9 | |
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| * | | | Merge pull request #2133 from dh73/nodev_head | Claire Xen | 2020-11-25 | 18 | -65/+322 | |
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| | * | | | Removing trailing whitespace | diego | 2020-06-10 | 1 | -30/+30 | |
| | * | | | Adding latch tests for shift&mask AST dynamic part-select enhancements | diego | 2020-06-09 | 18 | -68/+325 | |
| * | | | | Merge pull request #2442 from cr1901/sccache | whitequark | 2020-11-25 | 1 | -2/+7 | |
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| | * | | | | Makefile: Update ABCREV to bring in sccache fixes. | William D. Jones | 2020-11-24 | 1 | -1/+1 | |
| | * | | | | Makefile: Add disabled-by-default ENABLE_SCCACHE config option. | William D. Jones | 2020-11-19 | 1 | -1/+6 | |
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| * | | | | Merge pull request #2450 from nitz/sim-vcd-filename | whitequark | 2020-11-25 | 1 | -1/+3 | |
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| | * | | | | Add rewrite_filename for sim -vcd argument. | Chris Dailey | 2020-11-24 | 1 | -1/+3 | |
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| * | | | | Bump version | Yosys Bot | 2020-11-25 | 1 | -1/+1 | |
| * | | | | Merge pull request #2428 from whitequark/check-processes | whitequark | 2020-11-24 | 1 | -22/+55 | |
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| | * | | | | check: add support for processes. | whitequark | 2020-11-03 | 1 | -3/+38 | |
| | * | | | | check: reformat log/help text to match most other passes | whitequark | 2020-11-03 | 1 | -19/+17 | |
| * | | | | | Merge pull request #2448 from nitz/tcl-script-documentation-fixes | Miodrag Milanović | 2020-11-24 | 1 | -0/+2 | |
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| | * | | | | | tcl -h message only if YOSYS_ENABLE_TCL defined. | nitz | 2020-11-23 | 1 | -0/+2 | |
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| * | | | | | Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parameters | Miodrag Milanović | 2020-11-24 | 1 | -58/+294 | |
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| | * | | | | Formatting fixes | Sahand Kashani | 2020-11-23 | 1 | -10/+7 | |
| | * | | | | Add support for real-valued parameters + preserve type of parameters | Sahand Kashani | 2020-08-06 | 1 | -38/+113 | |
| | * | | | | Add firrtl backend support for generic parameters in blackbox components | Sahand Kashani | 2020-07-23 | 1 | -58/+222 | |
| * | | | | | Bump version | Yosys Bot | 2020-11-21 | 1 | -1/+1 | |
| * | | | | | Merge pull request #2443 from YosysHQ/dave/nexus-mult-infer | Miodrag Milanović | 2020-11-20 | 4 | -13/+151 | |
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| | * | | | | nexus: DSP inference support | David Shah | 2020-11-20 | 4 | -13/+151 | |
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| * | | | | Bump version | Yosys Bot | 2020-11-19 | 1 | -1/+1 | |
| * | | | | Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim | Miodrag Milanović | 2020-11-18 | 3 | -250/+573 | |
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| | * | | | | nexus: Add DSP simulation model | David Shah | 2020-11-18 | 3 | -250/+573 | |
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| * | | | | Fix duplicated parameter name typo | Miodrag Milanovic | 2020-11-18 | 1 | -1/+1 | |
| * | | | | Bump version | Yosys Bot | 2020-11-17 | 1 | -1/+1 | |
| * | | | | backends/blif: Remove unused vector of strings (#2420) | William Woodruff | 2020-11-16 | 1 | -57/+53 | |
| * | | | | Merge pull request #2438 from kbeckmann/gowin_rpll | Miodrag Milanović | 2020-11-16 | 1 | -0/+45 | |
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| | * | | | | synth_gowin: Add rPLL blackbox | Konrad Beckmann | 2020-11-11 | 1 | -0/+45 | |
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| * | | | | Bump version | Yosys Bot | 2020-11-11 | 1 | -1/+1 | |
| * | | | | Merge pull request #2433 from YosysHQ/paths_as_globals | Miodrag Milanović | 2020-11-10 | 4 | -43/+63 | |
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| | * | | | | Expose abc and data paths as globals | Miodrag Milanovic | 2020-11-06 | 4 | -43/+63 | |
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| * | | | | Bump version | Yosys Bot | 2020-11-08 | 1 | -1/+1 | |
| * | | | | Merge pull request #2414 from zeldin/abc-depend-clang-fix | whitequark | 2020-11-07 | 1 | -0/+4 | |
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index : iCE40/yosys | |
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