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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-11-18 10:03:57 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-11-18 10:03:57 +0100 |
| commit | aa4d94f7d8cd4c9e41552af5eacc9bb131bb2b2f (patch) | |
| tree | 81c1144c8c1f9b46fab78e3308e3089ecab3acdc | |
| parent | 58e8901fee7f4a7cc77e123d42ac817abf1d47f8 (diff) | |
| download | yosys-aa4d94f7d8cd4c9e41552af5eacc9bb131bb2b2f.tar.gz yosys-aa4d94f7d8cd4c9e41552af5eacc9bb131bb2b2f.tar.bz2 yosys-aa4d94f7d8cd4c9e41552af5eacc9bb131bb2b2f.zip | |
Fix duplicated parameter name typo
| -rw-r--r-- | techlibs/intel/common/m9k_bb.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/common/m9k_bb.v b/techlibs/intel/common/m9k_bb.v index b18a752f5..4bb230642 100644 --- a/techlibs/intel/common/m9k_bb.v +++ b/techlibs/intel/common/m9k_bb.v @@ -32,7 +32,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr parameter outdata_reg_a = "UNREGISTERED"; parameter operation_mode = "SINGLE_PORT"; parameter intended_device_family = "MAX 10 FPGA"; - parameter outdata_reg_a = "UNREGISTERED"; + parameter outdata_reg_b = "UNREGISTERED"; parameter lpm_type = "altsyncram"; parameter init_type = "unused"; parameter ram_block_type = "AUTO"; |