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* Merge branch 'master' of https://github.com/bogdanvuk/yosys into ↵Clifford Wolf2019-06-205-10/+423
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| * Move netlist helper module to passes/opt for the time beingBogdan Vukobratovic2019-06-142-1/+1
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| * Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-06-1473-475/+1352
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| * | Prepare for situation when port of the signal cannot be foundBogdan Vukobratovic2019-06-142-2/+8
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| * | Some cleanup, revert sat.ccBogdan Vukobratovic2019-06-142-13/+11
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| * | Implement disconnection of constant register bitsBogdan Vukobratovic2019-06-132-44/+109
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| * | Pass SigBit by value to Netlist algorithmsBogdan Vukobratovic2019-06-131-65/+84
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| * | Rename satgen_algo.h -> algo.h, code cleanup and refactoringBogdan Vukobratovic2019-06-124-279/+265
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| * | Generate satgen instance instead of calling sat passBogdan Vukobratovic2019-06-112-24/+129
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| * | Refactor driver map generationBogdan Vukobratovic2019-06-101-0/+158
| | | | | | | | | | | | | | | - Implement iterators over the driver map that enumerate signals and cells within the cones of the signal
| * | Fix the regressionBogdan Vukobratovic2019-05-281-1/+2
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| * | Merge remote-tracking branch 'upstream/master'Bogdan Vukobratovic2019-05-281-1/+11
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| * | | Optimizing DFFs whose initial value prevents their value from changingBogdan Vukobratovic2019-05-284-3/+78
| | | | | | | | | | | | | | | | | | | | This is a proof of concept implementation that invokes SAT solver via Pass::call method.
* | | | Fix typoClifford Wolf2019-06-201-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge branch 'towoe-unpacked_arrays'Clifford Wolf2019-06-202-1/+23
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| * | | | Add proper test for SV-style arraysClifford Wolf2019-06-203-6/+16
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-203-1/+13
|/| | | | | | | | | | | | | | | | | | | towoe-unpacked_arrays
| * | | | Unpacked array declaration using sizeTobias Wölfel2019-06-193-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
* | | | | Merge pull request #1111 from acw1251/help_summary_fixesEddie Hung2019-06-194-6/+6
|\ \ \ \ \ | | | | | | | | | | | | Fixed the help summary line for a few commands
| * | | | | Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
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| * | | | | Fixed the help summary line for a few commandsacw12512019-06-194-6/+6
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* | | | | Fix bug in #1078, add entry to CHANGELOGEddie Hung2019-06-192-3/+4
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* | | | | Merge pull request #1109 from YosysHQ/clifford/fix1106Clifford Wolf2019-06-196-9/+48
|\ \ \ \ \ | | | | | | | | | | | | Add "read_verilog -pwires" feature
| * | | | | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-196-9/+48
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-195-16/+92
|\ \ \ \ \ | | | | | | | | | | | | Improve handling of initial/default values
| * | | | | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Add defaultvalue attributeClifford Wolf2019-06-192-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-195-0/+8
|\ \ \ \ \ | | | | | | | | | | | | Support ~ in filename parsing
| * | | | | Support filename rewrite in backendsBen Widawsky2019-06-184-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | | | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on Linux only v2: Wrap functioanlity in ifndef _WIN32 (eddiehung) Find '~/' instead of '~' (cliffordwolf) Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | | | | Merge pull request #1104 from whitequark/case-semanticsClifford Wolf2019-06-192-1/+40
|\ \ \ \ \ \ | |/ / / / / |/| | | | | Clarify switch/case semantics in RTLIL
| * | | | | Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
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| * | | | | In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* | | | | Merge pull request #1086 from udif/pr_elab_sys_tasks2Clifford Wolf2019-06-182-3/+13
|\ \ \ \ \ | |/ / / / |/| | | | Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
| * | | | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
| | | | | | | | | | | | | | | | | | | | (within always/initial blocks)
* | | | | Add timescale and generated-by header to yosys-smtbmc MkVcdClifford Wolf2019-06-161-0/+2
| |_|_|/ |/| | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #829 from abdelrahmanhosny/masterSerge Bazanski2019-06-132-0/+46
|\ \ \ \ | |/ / / |/| | | Dockerfile for Yosys
| * | | address review commentsAbdelrahman2019-03-011-23/+9
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| * | | add dockerignore fileAbdelrahman2019-02-261-0/+13
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| * | | dockerize yosysAbdelrahman2019-02-261-0/+47
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* | | | Add some more commentsEddie Hung2019-06-101-1/+6
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* | | | Merge pull request #1082 from corecode/u4kDavid Shah2019-06-101-0/+24
|\ \ \ \ | | | | | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
| * | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
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* | | | Merge pull request #1078 from YosysHQ/eddie/muxcover_costsClifford Wolf2019-06-081-12/+42
|\ \ \ \ | | | | | | | | | | Allow muxcover costs to be changed
| * | | | Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
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* | | | | Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
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* | | | | Merge pull request #1079 from YosysHQ/eddie/fix_read_aigerClifford Wolf2019-06-0727-45/+128
|\ \ \ \ \ | | | | | | | | | | | | Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
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