| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | | More testing | Eddie Hung | 2019-05-03 | 2 | -2/+5 |
| | * | | | Fix spacing | Eddie Hung | 2019-05-03 | 1 | -6/+6 |
| | * | | | Add quick-and-dirty specify tests | Eddie Hung | 2019-05-03 | 2 | -0/+53 |
| | * | | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 40 | -405/+931 |
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| | * | | | | Add specify support to README | Clifford Wolf | 2019-04-23 | 1 | -0/+5 |
| | * | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 4 | -13/+23 |
| | * | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 3 | -24/+24 |
| | * | | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 9 | -6/+133 |
| | * | | | | Preserve $specify[23] cells | Clifford Wolf | 2019-04-23 | 1 | -1/+1 |
| | * | | | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 |
| | * | | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 4 | -76/+76 |
| | * | | | | Add $specify2/$specify3 support to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+47 |
| | * | | | | Add support for $assert/$assume/$cover to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+10 |
| | * | | | | Add CellTypes support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 2 | -0/+7 |
| | * | | | | Add InternalCellChecker support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 1 | -7/+21 |
| | * | | | | Checking and fixing specify cells in genRTLIL | Clifford Wolf | 2019-04-23 | 1 | -1/+15 |
| | * | | | | Un-break default specify parser | Clifford Wolf | 2019-04-23 | 1 | -0/+1 |
| | * | | | | Add specify parser | Clifford Wolf | 2019-04-23 | 5 | -33/+253 |
| | * | | | | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 |
| * | | | | | Merge pull request #975 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-05-06 | 3 | -13/+66 |
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| | * \ \ \ \ | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 | Clifford Wolf | 2019-05-06 | 35 | -290/+787 |
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| | * | | | | | | Further improve unused-detection for opt_clean driver-driver conflict warning | Clifford Wolf | 2019-05-03 | 1 | -5/+8 |
| | * | | | | | | Improve unused-detection for opt_clean driver-driver conflict warning | Clifford Wolf | 2019-05-03 | 1 | -21/+29 |
| | * | | | | | | Add additional test cases for for-loops | Clifford Wolf | 2019-05-01 | 1 | -0/+25 |
| | * | | | | | | Silently resolve completely unused cell-vs-const driver-driver conflicts | Clifford Wolf | 2019-05-01 | 1 | -2/+21 |
| | * | | | | | | Re-enable "final loop assignment" feature | Clifford Wolf | 2019-05-01 | 1 | -2/+0 |
| * | | | | | | | Merge pull request #871 from YosysHQ/verific_import | Clifford Wolf | 2019-05-06 | 4 | -44/+181 |
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| | * | | | | | | Add tests/various/chparam.sh | Clifford Wolf | 2019-05-06 | 1 | -0/+52 |
| | * | | | | | | Add "hierarchy -chparam" support for non-verific top modules | Clifford Wolf | 2019-05-03 | 1 | -12/+35 |
| | * | | | | | | log_warning_noprefix -> log_warning as per review | Eddie Hung | 2019-05-03 | 1 | -1/+1 |
| | * | | | | | | For hier_tree::Elaborate() also include SV root modules (bind) | Eddie Hung | 2019-05-03 | 1 | -23/+36 |
| | * | | | | | | Fix verific_parameters construction, use attribute to mark top netlists | Eddie Hung | 2019-05-03 | 2 | -8/+12 |
| | * | | | | | | WIP -chparam support for hierarchy when verific | Eddie Hung | 2019-05-03 | 3 | -19/+41 |
| | * | | | | | | verific_import() changes to avoid ElaborateAll() | Eddie Hung | 2019-05-03 | 1 | -15/+38 |
| * | | | | | | | Fix the other bison warning in ilang_parser.y | Clifford Wolf | 2019-05-06 | 1 | -1/+1 |
| * | | | | | | | Bugfix in peepopt_shiftmul.pmg | Clifford Wolf | 2019-05-06 | 1 | -0/+4 |
| * | | | | | | | Merge pull request #992 from bwidawsk/bison-fix | Clifford Wolf | 2019-05-06 | 1 | -1/+1 |
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| | * | | | | | | | verilog_parser: Fix Bison warning | Ben Widawsky | 2019-05-05 | 1 | -1/+1 |
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| * | | | | | | | Merge pull request #989 from YosysHQ/dave/abc_name_improve | Clifford Wolf | 2019-05-06 | 1 | -8/+21 |
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| | * | | | | | | | abc: Fix handling of postfixed names (e.g. for retiming) | David Shah | 2019-05-04 | 1 | -4/+4 |
| | * | | | | | | | abc: Improve name recovery | David Shah | 2019-05-04 | 1 | -4/+17 |
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| * | | | | | | | Fix bug in "expose -input" | Clifford Wolf | 2019-05-06 | 1 | -1/+1 |
| * | | | | | | | Cleanups in opt_clean | Clifford Wolf | 2019-05-06 | 1 | -47/+16 |
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| * | | | | | | Merge pull request #988 from YosysHQ/clifford/fix987 | Clifford Wolf | 2019-05-04 | 2 | -1/+5 |
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| | * | | | | | Add approximate support for SV "var" keyword, fixes #987 | Clifford Wolf | 2019-05-04 | 2 | -1/+5 |
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| * | | | | | Improve opt_clean handling of unused wires | Clifford Wolf | 2019-05-04 | 1 | -10/+22 |
| * | | | | | Add support for SVA "final" keyword | Clifford Wolf | 2019-05-04 | 2 | -1/+5 |
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| * | | | | Rename cells_map.v to prevent clash with ff_map.v | Eddie Hung | 2019-05-03 | 1 | -6/+8 |
| * | | | | iverilog with simcells.v as well | Eddie Hung | 2019-05-03 | 1 | -1/+2 |
| * | | | | Merge pull request #969 from YosysHQ/clifford/pmgenstuff | Clifford Wolf | 2019-05-03 | 13 | -151/+509 |
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