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author | Clifford Wolf <clifford@clifford.at> | 2015-06-17 09:38:56 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-06-17 09:38:56 +0200 |
commit | 99100f367d9239b4607a7fee05855a5f34be4467 (patch) | |
tree | d858fc477e922432708583ce687a8ac8b7a18479 | |
parent | 9f7a5b4ef92357761a3526fdc1c8171d8be9888c (diff) | |
download | yosys-99100f367d9239b4607a7fee05855a5f34be4467.tar.gz yosys-99100f367d9239b4607a7fee05855a5f34be4467.tar.bz2 yosys-99100f367d9239b4607a7fee05855a5f34be4467.zip |
Added "rename -top new_name"
-rw-r--r-- | kernel/rtlil.cc | 15 | ||||
-rw-r--r-- | kernel/rtlil.h | 1 | ||||
-rw-r--r-- | passes/cmds/rename.cc | 27 |
3 files changed, 43 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5deef8507..7cd2dd4bb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -316,6 +316,21 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) return modules_.count(name) ? modules_.at(name) : NULL; } +RTLIL::Module *RTLIL::Design::top_module() +{ + RTLIL::Module *module = nullptr; + int module_count = 0; + + for (auto mod : selected_modules()) { + if (mod->get_bool_attribute("\\top")) + return mod; + module_count++; + module = mod; + } + + return module_count == 1 ? module : nullptr; +} + void RTLIL::Design::add(RTLIL::Module *module) { log_assert(modules_.count(module->name) == 0); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e9deb1d5f..b6248c4c0 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -800,6 +800,7 @@ struct RTLIL::Design RTLIL::ObjRange<RTLIL::Module*> modules(); RTLIL::Module *module(RTLIL::IdString name); + RTLIL::Module *top_module(); bool has(RTLIL::IdString id) const { return modules_.count(id) != 0; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 17d803e96..d16713175 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -76,12 +76,17 @@ struct RenamePass : public Pass { log("Assign private names (the ones with $-prefix) to all selected wires and cells\n"); log("with public names. This ignores all selected ports.\n"); log("\n"); + log(" rename -top new_name\n"); + log("\n"); + log("Rename top module.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { std::string pattern_prefix = "_", pattern_suffix = "_"; bool flag_enumerate = false; bool flag_hide = false; + bool flag_top = false; bool got_mode = false; size_t argidx; @@ -98,6 +103,11 @@ struct RenamePass : public Pass { got_mode = true; continue; } + if (arg == "-top" && !got_mode) { + flag_top = true; + got_mode = true; + continue; + } if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) { int pos = args[++argidx].find('%'); pattern_prefix = args[argidx].substr(0, pos); @@ -171,6 +181,23 @@ struct RenamePass : public Pass { } } else + if (flag_top) + { + if (argidx+1 != args.size()) + log_cmd_error("Invalid number of arguments!\n"); + + IdString new_name = RTLIL::escape_id(args[argidx]); + RTLIL::Module *module = design->top_module(); + + if (module == NULL) + log_cmd_error("No top module found!\n"); + + log("Renaming module %s to %s.\n", log_id(module), log_id(new_name)); + design->modules_.erase(module->name); + module->name = new_name; + design->modules_[module->name] = module; + } + else { if (argidx+2 != args.size()) log_cmd_error("Invalid number of arguments!\n"); |