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* Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
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* FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
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* Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
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* Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
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* write_xaiger: be more precise with ff_bits, remove ff_aig_mapEddie Hung2019-12-311-21/+19
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* Retry getting rid of write_xaiger's holes_modeEddie Hung2019-12-311-81/+41
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* Revert "Get rid of holes_mode"Eddie Hung2019-12-301-35/+70
| | | | This reverts commit 7997e2a90fd37886241b7eb657408177ef7f6fa7.
* Get rid of holes_modeEddie Hung2019-12-301-70/+35
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* Add -D DFF_MODE to abc9_map testEddie Hung2019-12-301-4/+4
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* Remove delay targets docEddie Hung2019-12-301-9/+0
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* write_xaiger to use scratchpad for stats; cleanup abc9Eddie Hung2019-12-302-190/+20
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* Remove submod changesEddie Hung2019-12-302-201/+37
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* Remove unusedEddie Hung2019-12-301-5/+0
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* Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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* Call "proc" if processes inside whiteboxesEddie Hung2019-12-301-1/+1
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3042-211/+1731
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| * Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-3020-71/+67
| |\ | | | | | | Make iopad option default for all xilinx flows
| | * Fix new testsMiodrag Milanovic2019-12-283-6/+6
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| | * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-2820-150/+1614
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| | * | Make test without iopadsMiodrag Milanovic2019-12-2817-51/+51
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| | * | Revert "Fix xilinx tests, when iopads are default"Miodrag Milanovic2019-12-2816-40/+40
| | | | | | | | | | | | | | | | This reverts commit 477e43d921d204c6bc6403109fea6506802c948c.
| | * | Addressed review commentsMiodrag Milanovic2019-12-212-3/+3
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| | * | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
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| | * | Fix xilinx tests, when iopads are defaultMiodrag Milanovic2019-12-2117-42/+44
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| | * | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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| * | | Merge pull request #1599 from YosysHQ/eddie/retry_1588Eddie Hung2019-12-304-20/+87
| |\ \ \ | | | | | | | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
| | * | | Add #1598 testcaseEddie Hung2019-12-273-0/+48
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| | * | | write_xaiger: inherit port ordering from original moduleEddie Hung2019-12-271-5/+16
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| | * | | Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"Eddie Hung2019-12-271-19/+27
| | | |/ | | |/| | | | | | | | | | | | | This reverts commit 92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing changes made to 3e14ff16676884a1f65cf0eeb0ca9cb1958b8804.
| * | | Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5Eddie Hung2019-12-303-14/+6
| |\ \ \ | | |/ / | |/| | Nitpick cleanup for ecp5
| | * | Update resource countEddie Hung2019-12-281-3/+3
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| | * | Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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| * | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-271-27/+19
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| | * \ Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanupDavid Shah2019-12-271-27/+19
| | |\ \ | | | | | | | | | | Revert "write_xaiger: only instantiate each whitebox cell type once"
| | | * | Revert "write_xaiger: only instantiate each whitebox cell type once"David Shah2019-12-271-27/+19
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| * / / write_xaiger: simplify c{i,o}_bitsEddie Hung2019-12-271-12/+6
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| * | fixed invalid charMiodrag Milanovic2019-12-251-1/+1
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| * | iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-252-23/+91
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| * | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-2512-81/+1136
| |\ \ | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| | * | Minor nit fixesMarcin Kościelnicki2019-12-251-2/+2
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| | * | Add DSP cascade testsEddie Hung2019-12-231-0/+89
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| | * | Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG tooEddie Hung2019-12-231-8/+18
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| | * | Fix CEA/CEB checkEddie Hung2019-12-231-2/+2
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| | * | Fix checking CE[AB] and for direct connectionsEddie Hung2019-12-231-18/+40
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| | * | Support unregistered cascades for A and B inputsEddie Hung2019-12-231-47/+74
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| | * | Add DSP48A* PCOUT -> PCIN cascade supportEddie Hung2019-12-231-10/+10
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| | * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-2210-14/+921
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| * / xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
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| * Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-201-19/+27
| |\ | | | | | | write_xaiger: only instantiate each whitebox cell type once
| | * write_xaiger: only instantiate each whitebox cell type onceEddie Hung2019-12-201-19/+27
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