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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 15:24:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 15:24:02 -0800 |
| commit | 4cdba00e25d892b90c0ee48716c17dec60e472db (patch) | |
| tree | 6f85162ff0715af2cf03c7d835119a95c0d6d8c0 | |
| parent | b4663a987bc1bac3aa4cccab99dc191825902205 (diff) | |
| download | yosys-4cdba00e25d892b90c0ee48716c17dec60e472db.tar.gz yosys-4cdba00e25d892b90c0ee48716c17dec60e472db.tar.bz2 yosys-4cdba00e25d892b90c0ee48716c17dec60e472db.zip | |
FDCE ports to be alphabetical
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 4d20e1d2c..982ccad72 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -405,10 +405,10 @@ module FDCE ( (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_D_INVERTED" *) - input D, (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR + input CLR, + (* invertible_pin = "IS_D_INVERTED" *) + input D ); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; |