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* remove whitespaceMiodrag Milanovic2020-02-141-1/+1
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* Add expect option to logger commandMiodrag Milanovic2020-02-144-3/+113
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* Add new logger passMiodrag Milanovic2020-02-132-0/+142
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* abc9: cleanupEddie Hung2020-02-102-41/+41
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* Merge pull request #1670 from rodrigomelo9/masterEddie Hung2020-02-107-3/+152
|\ | | | | $readmem[hb] file inclusion is now relative to the Verilog file
| * Added 'set -e' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-061-0/+20
| | | | | | | | | | | | Also added two checks for situations where the execution must fail. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
| | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * Merge branch 'master' into masterRodrigo A. Melo2020-02-0310-4/+367
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| * \ Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-0312-112/+369
| |\ \ | | | | | | | | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | Replaced strlen by GetSize into simplify.ccRodrigo Alejandro Melo2020-02-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As recommended in CodingReadme. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | Removed 'synth' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-021-8/+8
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | Added content1.dat into tests/memfileRodrigo Alejandro Melo2020-02-022-21/+81
| | | | | | | | | | | | | | | | | | | | | | | | Modified run-test.sh to use it. Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | Removed a line jump into the CHANGELOGRodrigo Alejandro Melo2020-02-011-3/+2
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | Added tests/memfile to 'make test' with an extra testcaseRodrigo Alejandro Melo2020-02-012-16/+11
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | Added a test for the Memory Content File inclusion using $readmembRodrigo Alejandro Melo2020-02-013-0/+63
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-312-2/+4
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | | | Merge pull request #1669 from thasti/pyosys-attrsN. Engelhardt2020-02-101-2/+38
|\ \ \ \ | | | | | | | | | | Make RTLIL attributes accessible via pyosys
| * | | | remove namespace mention from inheritance informationStefan Biereigel2020-02-031-1/+1
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| * | | | expose polymorphism through python wrappersStefan Biereigel2020-02-031-2/+8
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| * | | | add inheritance for pywrap generatorsStefan Biereigel2020-01-301-0/+30
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* | | | | Merge pull request #1695 from whitequark/manual-explain-wire-upto-offsetwhitequark2020-02-091-0/+7
|\ \ \ \ \ | | | | | | | | | | | | manual: explain RTLIL::Wire::{upto,offset}
| * | | | | manual: explain RTLIL::Wire::{upto,offset}.whitequark2020-02-091-0/+7
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* | | | | Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* | | | | Merge pull request #1687 from YosysHQ/eddie/fix_ystestsEddie Hung2020-02-072-9/+7
|\ \ \ \ \ | | | | | | | | | | | | Fix shiftx2mux, fix yosys-tests
| * | | | | techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
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| * | | | | Fix misc.abc9.abc9_abc9_lutsEddie Hung2020-02-071-1/+1
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* | | | | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-075-27/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* | | | | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-076-54/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* | | | | Merge pull request #1685 from dh73/gowinEddie Hung2020-02-061-1/+1
|\ \ \ \ \ | | | | | | | | | | | | Removing cells_sim from GoWin bram techmap
| * | | | | Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
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* | | | | | Merge pull request #1683 from whitequark/write_verilog-memattrswhitequark2020-02-071-0/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | write_verilog: dump $mem cell attributes
| * | | | | | write_verilog: dump $mem cell attributes.whitequark2020-02-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Verilog backend already dumps attributes on RTLIL::Memory objects but not on `$mem` cells.
* | | | | | | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
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* | | | | | | xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-073-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of #1550
* | | | | | | Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_mapEddie Hung2020-02-061-109/+43
|\ \ \ \ \ \ \ | |_|/ / / / / |/| | | | | | Fix/cleanup +/xilinx/arith_map.v
| * | | | | | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwkEddie Hung2020-02-061-4/+5
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| * | | | | | Fix/cleanup +/xilinx/arith_map.vEddie Hung2020-02-061-111/+44
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* | | | | | | edif: more resilience to mismatched port connection sizes.Marcin Kościelnicki2020-02-061-16/+27
| |/ / / / / |/| | | | | | | | | | | | | | | | | Fixes #1653.
* | | | | | Merge pull request #1682 from YosysHQ/eddie/opt_after_techmapEddie Hung2020-02-058-5/+9
|\ \ \ \ \ \ | | | | | | | | | | | | | | synth_*: call 'opt -fast' after 'techmap'
| * | | | | | synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-058-5/+9
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* / / / / / shiftx2mux: fix select out of boundsEddie Hung2020-02-053-2/+14
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* | | | | Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-052-1/+65
|\ \ \ \ \ | | | | | | | | | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-28190-4933/+9266
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| * | | | | | Add $_FF_ and $_SR* courtesy of @mwkmwkmwkEddie Hung2019-12-202-23/+33
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| * | | | | | More stringent check for flop cellsEddie Hung2019-12-201-2/+4
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| * | | | | | opt_merge to discard \init of '$' cells with 'Q' port when mergingEddie Hung2019-12-131-0/+11
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| * | | | | | Add testcaseEddie Hung2019-12-131-0/+49
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* | | | | | | Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-054-39/+185
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | techmap LSB-first for compatible $shift/$shiftx cells
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