aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
| | | |
| * | | Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
| | | |
* | | | Merge pull request #551 from olofk/ice40_cells_sim_portsClifford Wolf2018-05-171-43/+23
|\ \ \ \ | |/ / / |/| | | Avoid mixing module port declaration styles in ice40 cells_sim.v
| * | | Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
|/ / / | | | | | | | | | | | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax.
* | | Fix handling of anyconst/anyseq attrs in VHDL code via VerificClifford Wolf2018-05-151-6/+6
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Remove mercurial from build instructionsClifford Wolf2018-05-151-3/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix iopadmap for loops between tristate IO buffersClifford Wolf2018-05-151-0/+21
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix iopadmap for cases where IO pins already have buffers on themClifford Wolf2018-05-151-1/+35
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Correction to -expose with setundefAman Goel2018-05-151-0/+1
| | |
| | * Minor correctionAman Goel2018-05-141-2/+1
| | | | | | | | | | | | Minor typo error correction in -expose with setundef
| | * Corrections to option -expose in setundef passAman Goel2018-05-131-16/+141
| | |
| | * Add option -expose to setundef passAman Goel2018-05-131-6/+26
| |/ |/| | | | | | | | | Option -expose converts undriven wires to inputs. Example usage: setundef -undriven -expose [selection]
* | Some cleanups in setundef.ccClifford Wolf2018-05-131-0/+7
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Use $(OS) in makefile to check for DarwinClifford Wolf2018-05-131-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #505 from thefallenidealist/FreeBSD_buildClifford Wolf2018-05-133-2/+26
|\ \ | | | | | | FreeBSD build
| * | update READMEJohnny Sorocil2018-05-061-0/+8
| | |
| * | autotest.sh: Change from /bin/bash to /usr/bin/env bashJohnny Sorocil2018-05-061-1/+1
| | | | | | | | | | | | | | | This enables running tests on Unix systems which are not shipped with bash installed in /bin/bash (eg *BSDs and Solaris).
| * | Enable building on FreeBSDJohnny Sorocil2018-05-061-1/+17
| | |
* | | Add "#ifdef __FreeBSD__"Christian Krämer2018-05-135-9/+52
| | | | | | | | | | | | (Re-commit e3575a8 with corrected author field)
* | | Revert "Add "#ifdef __FreeBSD__""Clifford Wolf2018-05-135-52/+9
| | | | | | | | | | | | This reverts commit e3575a86c525f2511902e7022893c3923ba8093e.
* | | Also interpret '&' in liberty functionsSergiusz Bazanski2018-05-121-1/+1
| | |
* | | Add optimization of tristate buffer with constant control inputClifford Wolf2018-05-121-0/+17
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "hierarchy -simcheck"Clifford Wolf2018-05-121-7/+23
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Further improve handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-69/+108
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-26/+46
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "#ifdef __FreeBSD__"Johnny Sorocil2018-05-055-9/+52
| |
* | Add ABC FAQ to "help abc"Clifford Wolf2018-05-041-2/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "yosys -e regex" for turning warnings into errorsClifford Wolf2018-05-043-4/+22
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
|\ \ | | | | | | Improving Yosys when used with VPR
| * | Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| | | | | | | | | | | | | | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
| * | synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
| | |
* | | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-035-21/+58
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Support more character literalsDan Gisselquist2018-05-031-1/+9
| | |
* | | Update ABC to git rev f23ea8eClifford Wolf2018-04-301-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "write_blif -inames -iattr"Clifford Wolf2018-04-151-22/+46
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve Makefile error handling for when abc/ is a hg working copyClifford Wolf2018-04-121-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add PRIM_HDL_ASSERTION support to Verific importerClifford Wolf2018-04-071-3/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of $global_clocking in VerificClifford Wolf2018-04-061-1/+7
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add documentation for anyconst/anyseq/allconst/allseq attributeClifford Wolf2018-04-061-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add Verific anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-2/+36
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "verific -autocover"Clifford Wolf2018-04-062-5/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #530 from makaimann/set-ram-flagsClifford Wolf2018-04-061-0/+3
|\ \ | | | | | | Set RAM runtime flags for Verific frontend
| * | Set RAM runtime flags for Verific frontendmakaimann2018-04-051-0/+3
|/ /
* | Added missing dont_use handling for SR FFs to dfflibmapClifford Wolf2018-04-051-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-25 21:01:44 +0000