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* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-042-10/+15
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* Merge pull request #2738 from mdko/xilinx-blifMiodrag Milanović2021-04-271-1/+1
|\ | | | | Fix use of blif name in synth_xilinx command
| * Fix use of blif name in synth_xilinx commandMichael Christensen2021-04-271-1/+1
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* Merge pull request #2737 from YosysHQ/claire/fix2736Claire Xen2021-04-261-0/+4
|\ | | | | Remove duplicates from conns array in JSON front-end, fixes #2736
| * Remove duplicates from conns array in JSON front-end, fixes #2736Claire Xenia Wolf2021-04-261-0/+4
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* Merge pull request #2669 from YosysHQ/claire/ice40defaultsClaire Xen2021-04-212-26/+62
|\ | | | | Add input default assignments to iCE40 cell library
| * Add default assignments to other SB_* simulation modelsClaire Xenia Wolf2021-04-201-24/+44
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-202-2/+18
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* quicklogic: ABC9 synthesisLofty2021-04-1712-22/+97
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* sf2: fix name of AND modulesStefan Riesenberger2021-04-091-3/+3
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* Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memidwhitequark2021-04-091-0/+3
|\ | | | | flatten: rewrite memid in memwr actions
| * flatten: rewrite memid in memwr actions.whitequark2021-04-091-0/+3
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* preproc: test coverage for #2712Zachary Snow2021-03-303-0/+18
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* equiv: Suggest running async2sync or clk2fflogic where appropriate.Marcelina Kościelnicka2021-03-302-3/+10
| | | | See #2713.
* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
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* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-292-11/+62
| | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-299-45/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* Bump versionMarcelina Kościelnicka2021-03-301-1/+1
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* preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
| | | | | Fixes #2710. Fixes #2711.
* gha: trim macOS dependenciesZachary Snow2021-03-281-3/+1
| | | | | | - Only install needed dependencies rather than using Brewfile - Remove brew update (recent enough formulae already baked in) - Saves ~16 minutes in macOS CI
* gha: combine jobs using matrixZachary Snow2021-03-281-43/+24
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* rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-252-0/+15
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* Merge pull request #2702 from modwizcode/patch-1whitequark2021-03-241-0/+2
|\ | | | | Clarify bugpoint documentation regarding output
| * Clarify bugpoint documentation regarding outputIris Johnson2021-03-241-0/+2
|/ | | | | | | Bugpoint's current documentation does specify that the result of a run is stored as the current design, however it's easy to skim over what that means in practice. Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save the reduced design.
* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
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* rtlil: Fix process memwr roundtrip.Marcelina Kościelnicka2021-03-231-1/+1
| | | | Fixes #2646 fallout.
* Merge pull request #2696 from nakengelhardt/guidelinesN. Engelhardt2021-03-2311-318/+295
|\ | | | | split CodingReadme into multiple files
| * split CodingReadme into multiple filesN. Engelhardt2021-03-2211-318/+295
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* | quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
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* | json: Improve the "processes in module" message a bit.Marcelina Kościelnicka2021-03-231-1/+1
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* verilog: check entire user type stack for type definitionXiretza2021-03-212-6/+22
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* sv: allow typenames as function return typesZachary Snow2021-03-193-0/+46
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* Merge pull request #2681 from msinger/fix-issue2606Miodrag Milanović2021-03-191-3/+23
|\ | | | | Fix check for bad std::regex
| * Fix check for bad std::regex (fixes #2606)Michael Singer2021-03-171-3/+23
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* | verilog: rebuild user_type_stack from globals before parsing fileXiretza2021-03-181-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | This was actually a ticking UB bomb: after running the parser, the type maps contain pointers to children of the current AST, which is recursively deleted after the pass has executed. This leaves the pointers in user_type_stack dangling, which just happened to never be a problem due to another bug that causes typedefs from higher-level type maps to never be considered. Rebuilding the type stack from the design's globals ensures the AstNode pointers are valid.
* | Add simple CI using github actions.Marcelina Kościelnicka2021-03-181-0/+87
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* | modtools: fix use-after-free of cell pointers in ModWalkerXiretza2021-03-181-0/+2
| | | | | | | | | | | | | | | | cell_inputs and cell_outputs retain cell pointers as their keys across invocations of setup(), which may however be invalidated in the meantime (as happens in e.g. passes/opt/share.cc:1432). A later rehash of the dicts (caused by inserting in ModWalker::add_wire()) will cause them to be dereferenced.
* | quicklogic: PolarPro 3 supportLofty2021-03-1820-0/+1033
| | | | | | | | | | | | | | | | Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
* | ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-182-5/+28
|/ | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* Blackbox all whiteboxes after synthesisgatecat2021-03-1716-9/+24
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* bugpoint: add runner optionZachary Snow2021-03-172-6/+20
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* sv: carry over global typedefs from previous filesZachary Snow2021-03-173-2/+65
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-172-4/+30
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* blackbox: Include whiteboxed modulesgatecat2021-03-174-4/+19
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace assert in get_reference with more useful error messageLofty2021-03-171-1/+2
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* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-162-4/+37
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* json: Add support for memories.Marcelina Kościelnicka2021-03-152-0/+88
| | | | | | | | | | | | | | Previously, memories were silently discarded by the JSON backend, making round-tripping modules with them crash. Since there are already some users using JSON to implement custom external passes that use memories (and infer width/size from memory ports), let's fix this by just making JSON backend and frontend support memories as first-class objects. Processes are still not supported, and will now cause a hard error. Fixes #1908.
* proc_arst: Add special-casing of clock signal in conditionals.Marcelina Kościelnicka2021-03-152-23/+82
| | | | | | | | | | | | | | | | | The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656.
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-152-11/+24
| | | | Fixes #2546.
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-152-18/+63
| | | | | | | | | Among other problems, this also fixes equality comparisons between SigSpec by enforcing a canonical form. Also fix another minor issue with possible non-canonical SigSpec. Fixes #2623.
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