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* Add "yosys -e regex" for turning warnings into errorsClifford Wolf2018-05-043-4/+22
* Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
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| * Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| * synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-035-21/+58
* | Support more character literalsDan Gisselquist2018-05-031-1/+9
* | Update ABC to git rev f23ea8eClifford Wolf2018-04-301-1/+1
* | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
* | Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
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* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
* Add "write_blif -inames -iattr"Clifford Wolf2018-04-151-22/+46
* Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
* Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
* Improve Makefile error handling for when abc/ is a hg working copyClifford Wolf2018-04-121-0/+3
* Add PRIM_HDL_ASSERTION support to Verific importerClifford Wolf2018-04-071-3/+19
* Fix handling of $global_clocking in VerificClifford Wolf2018-04-061-1/+7
* Add documentation for anyconst/anyseq/allconst/allseq attributeClifford Wolf2018-04-061-0/+4
* Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
* Add Verific anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-2/+36
* Add "verific -autocover"Clifford Wolf2018-04-062-5/+17
* Merge pull request #530 from makaimann/set-ram-flagsClifford Wolf2018-04-061-0/+3
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| * Set RAM runtime flags for Verific frontendmakaimann2018-04-051-0/+3
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* Added missing dont_use handling for SR FFs to dfflibmapClifford Wolf2018-04-051-0/+4
* Create issue_template.mdClifford Wolf2018-04-041-0/+16
* Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constantsClifford Wolf2018-04-041-0/+3
* Fixed -stbv handling in SMT2 back-endClifford Wolf2018-04-041-1/+1
* Merge pull request #522 from c60k28/masterClifford Wolf2018-04-0111-178/+233
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| * Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...c60k282018-03-3111-178/+233
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* Remove left-over log_ping debug commands.. oops.Clifford Wolf2018-03-311-4/+0
* Merge pull request #521 from azonenberg/for_cliffordClifford Wolf2018-03-314-0/+113
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| * coolrunner2: Add an ANDTERM/XOR between chained FFsRobert Ou2018-03-311-0/+58
| * coolrunner2: Split multi-bit netsRobert Ou2018-03-311-0/+1
| * coolrunner2: Add extraction for TFFsRobert Ou2018-03-313-0/+54
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* Add smtio status msgs when --progress is inactiveClifford Wolf2018-03-291-2/+23
* Bugfix in smtio.py VCD file generatorClifford Wolf2018-03-291-1/+1
* Removed $timescale from "sat" command VCD writerClifford Wolf2018-03-291-1/+0
* Set stack size to at least 128 MB (large stack needed for parsing huge expres...Clifford Wolf2018-03-271-0/+13
* Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
* First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-273-2/+201
* Merge pull request #515 from edcote/patch-1Clifford Wolf2018-03-271-3/+5
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| * Rename rename to renamesEdmond Cote2018-03-201-3/+5
* | Chenged "extensions_map" to "extensions_list" in hierarchy.ccClifford Wolf2018-03-271-2/+2
* | Merge pull request #518 from xerpi/masterClifford Wolf2018-03-271-15/+13
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| * | passes/hierarchy: Reduce code duplication in expand_moduleSergi Granell2018-03-271-15/+13
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* | Add $mem support to SMT2 clock taggingClifford Wolf2018-03-271-0/+18
* | Fix build for new ABC location on github, also update ABC to a2d59beClifford Wolf2018-03-271-6/+6
* | Add .sv support to "hierarchy -libdir"Clifford Wolf2018-03-261-0/+6
* | Fix handling of unclocked immediate assertions in Verific front-endClifford Wolf2018-03-263-17/+42
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* Improve yosys-smtbmc log output and error handlingClifford Wolf2018-03-171-5/+14
* Improve handling of invalid check-sat result in smtio.pyClifford Wolf2018-03-171-1/+2
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