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Age
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Output pattern matcher items as log_debug()
Eddie Hung
2019-09-20
2
-31
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+27
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OPMODE is port not param
Eddie Hung
2019-09-20
1
-7
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+6
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-20
4
-18
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+50
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Merge pull request #1386 from YosysHQ/clifford/fix1360
Clifford Wolf
2019-09-20
2
-18
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+30
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Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #...
Clifford Wolf
2019-09-20
2
-18
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+30
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Update CHANGELOG
Clifford Wolf
2019-09-20
1
-0
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+2
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Add "add -mod"
Clifford Wolf
2019-09-20
1
-0
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+18
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Merge pull request #1384 from YosysHQ/clifford/fix1381
Clifford Wolf
2019-09-20
1
-5
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+49
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Do not run xilinx_dsp_cascadeAB for now
Eddie Hung
2019-09-20
1
-1
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+2
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WIP for xiinx_dsp_cascadeAB
Eddie Hung
2019-09-20
1
-3
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+499
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Run until convergence
Eddie Hung
2019-09-20
1
-3
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+9
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Cleanup ice40_dsp.pmg
Eddie Hung
2019-09-20
1
-12
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+6
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Cleanup xilinx_dsp
Eddie Hung
2019-09-20
1
-1
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+1
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More exceptions
Eddie Hung
2019-09-20
1
-2
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+2
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Fix signedness bug
Eddie Hung
2019-09-20
1
-2
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+2
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Update doc
Eddie Hung
2019-09-20
1
-2
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+2
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Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
Eddie Hung
2019-09-20
4
-54
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+105
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Add an overload for port/param with default value
Eddie Hung
2019-09-20
1
-0
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+8
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Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung
2019-09-20
2
-3
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+2
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Revert "Move mul2dsp before wreduce"
Eddie Hung
2019-09-20
1
-4
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+5
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Move mul2dsp before wreduce
Eddie Hung
2019-09-20
1
-5
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+4
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Small cleanup
Eddie Hung
2019-09-20
1
-19
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+18
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Disable support for SB_MAC16 reset since it is async
Eddie Hung
2019-09-19
2
-3
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+7
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SB_MAC16 ffCD to not pack same as ffO
Eddie Hung
2019-09-19
1
-2
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+2
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Add more complicated macc testcase
Eddie Hung
2019-09-19
2
-5
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+39
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Clarify
Eddie Hung
2019-09-19
1
-1
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+2
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Update doc for ice40_dsp
Eddie Hung
2019-09-19
1
-1
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+10
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Tidy up, fix undriven
Eddie Hung
2019-09-19
1
-32
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+34
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Add an index
Eddie Hung
2019-09-19
2
-0
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+3
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$__ABC_REG to have WIDTH parameter
Eddie Hung
2019-09-19
2
-17
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+18
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Fix DSP48E1 timing by breaking P path if MREG or PREG
Eddie Hung
2019-09-19
4
-349
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+363
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Revert "Different approach to timing"
Eddie Hung
2019-09-19
4
-195
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+405
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Different approach to timing
Eddie Hung
2019-09-19
4
-405
/
+195
*
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Fix width of D
Eddie Hung
2019-09-19
1
-1
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+1
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Add mac.sh and macc_tb.v for testing
Eddie Hung
2019-09-19
2
-0
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+99
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Suppress $anyseq warnings
Eddie Hung
2019-09-19
1
-15
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+32
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Use ID() macro
Eddie Hung
2019-09-19
2
-210
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+210
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Use (* techmap_autopurge *) to suppress techmap warnings
Eddie Hung
2019-09-19
2
-94
/
+99
*
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D is 25 bits not 24 bits wide
Eddie Hung
2019-09-19
1
-1
/
+1
*
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Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung
2019-09-19
14
-95
/
+723
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*
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Add techmap_autopurge attribute, fixes #1381
Clifford Wolf
2019-09-19
1
-5
/
+49
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/
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Use extractinv for synth_xilinx -ise
Marcin Kościelnicki
2019-09-19
8
-90
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+502
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Added extractinv pass
Marcin Kościelnicki
2019-09-19
5
-0
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+172
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Document (* gentb_skip *) attr for test_autotb
Eddie Hung
2019-09-18
1
-0
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+3
*
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When two boxes connect to each other, need not be a (* keep *)
Eddie Hung
2019-09-19
1
-6
/
+1
*
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Re-enable sign extension for C input
Eddie Hung
2019-09-19
1
-4
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+4
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synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
Eddie Hung
2019-09-19
1
-1
/
+4
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Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
Eddie Hung
2019-09-19
1
-1
/
+3
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Do not perform width-checks for DSP48E1 which is much more complicated
Eddie Hung
2019-09-19
1
-11
/
+0
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Remove TODO as check should not be necessary
Eddie Hung
2019-09-19
1
-1
/
+0
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