aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Added tcl "yosys -import" commandClifford Wolf2013-05-021-3/+29
|
* Improved/simplified TCL bindingsClifford Wolf2013-05-013-40/+57
|
* Added support for const cell inputs in techmapClifford Wolf2013-04-271-6/+28
|
* Fixed README for new show command behavior (svg vs. ps)Clifford Wolf2013-04-271-2/+6
|
* Added "flatten" passClifford Wolf2013-04-261-1/+41
|
* Fixed handling of positional module parametersClifford Wolf2013-04-261-6/+4
|
* Fixed hierarchy pass for hierarchies of parametric modulesClifford Wolf2013-04-261-0/+1
|
* Only use sha1 checksums for names of parametric modules when the verbose ↵Clifford Wolf2013-04-261-9/+20
| | | | form is to long
* Fixed "show -format ..." command line parsingClifford Wolf2013-04-151-1/+1
|
* Added "submod -name ..." supportClifford Wolf2013-04-151-40/+96
|
* Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵Clifford Wolf2013-04-132-4/+23
| | | | as case values
* Fixed a bug in opt_const when optimizing 1-bit compares with constantsClifford Wolf2013-04-131-2/+4
|
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-04-071-8/+40
|\
| * Merge pull request #5 from hansiglaser/masterClifford Wolf2013-04-051-6/+23
| |\ | | | | | | fsm_export: optionally use binary state encoding as state names instead of s0, s1, ...
| | * fsm_export: optionally use binary state encoding as state names instead ofJohann Glaser2013-04-051-6/+23
| | | | | | | | | | | | s0, s1, ...
| * | Merge pull request #4 from hansiglaser/masterClifford Wolf2013-04-051-5/+20
| |\| | | | | | | fsm_export: specify KISS filename on command line
| | * fsm_export: specify KISS filename on command lineJohann Glaser2013-04-051-5/+20
| |/
* / Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-071-4/+4
|/
* Fixed/improved handling of colored wires in show commandClifford Wolf2013-04-011-2/+2
|
* Added support for @<set-name> in expand select ops (%x, %ci, %co)Clifford Wolf2013-04-011-2/+12
|
* Removed 4096 bytes limit for size of command from script fileClifford Wolf2013-04-011-3/+20
|
* Added -color <color> <selection> option to show commandClifford Wolf2013-04-014-22/+101
|
* Fixed "select" for "%%" stmt with emty stackClifford Wolf2013-03-311-1/+2
|
* Added "script" commandClifford Wolf2013-03-311-0/+16
|
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-315-21/+32
|
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-315-3/+15
|
* Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-316-0/+111
|
* Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-313-0/+61
|
* Improved opt_share for reduce cellsClifford Wolf2013-03-293-3/+32
|
* Improved opt_share for commutative standard cellsClifford Wolf2013-03-291-1/+28
|
* Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-282-2/+3
|
* Improved Makefile: Added ENABLE_* switchesClifford Wolf2013-03-281-8/+24
|
* Implemented TCL support (only via -c option at the moment)Clifford Wolf2013-03-285-9/+83
|
* Improved subcircuit verbose output (added portmapper results)Clifford Wolf2013-03-281-0/+15
|
* Fixed svgviewer hacks for builtin filesClifford Wolf2013-03-281-8/+9
|
* Added proper TECHMAP_FAIL support and added support for the celltype ↵Clifford Wolf2013-03-281-84/+129
| | | | attribute in the map file
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-287-16/+70
|
* Keep viewport transform stable on reload in yosys-svgviewerClifford Wolf2013-03-272-4/+8
|
* Added check: only one module for "show" unless format is "ps"Clifford Wolf2013-03-271-0/+9
|
* Now using SVG and yosys-svgviewer per default in show commandClifford Wolf2013-03-274-16/+67
|
* Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlibClifford Wolf2013-03-274-5/+18
|
* Imported svgviewer from qt4.8Clifford Wolf2013-03-2711-0/+994
| | | | | This is from commit 543486a41963f8d20d9771d2107cdd5a22894bdb in the Qt git repository: git://gitorious.org/qt/qt.git
* Create nice errors when calling RTLIL::Module::derive() of base classClifford Wolf2013-03-261-3/+3
|
* Collect parameters in hierarchy -generate (and do nothing with them)Clifford Wolf2013-03-261-1/+8
|
* Tiny bugfix in simlib.vClifford Wolf2013-03-261-1/+0
|
* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-262-4/+2
|
* Fixed handling of unconditional generate blocksClifford Wolf2013-03-262-1/+19
|
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-255-34/+27
|
* Improved verbose output of subcircuitClifford Wolf2013-03-251-1/+11
|
* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-251-5/+7
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 03:00:20 +0000