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| author | Clifford Wolf <clifford@clifford.at> | 2013-04-26 13:28:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-04-26 13:28:15 +0200 |
| commit | 94744ac7b0238048869f04ea36cc35314798a70b (patch) | |
| tree | 4392c6e54b1967d5d5832f2cfde0ffcf8b382242 | |
| parent | 453a29c9f6704e49297f507d98bcccafe6f2fa59 (diff) | |
| download | yosys-94744ac7b0238048869f04ea36cc35314798a70b.tar.gz yosys-94744ac7b0238048869f04ea36cc35314798a70b.tar.bz2 yosys-94744ac7b0238048869f04ea36cc35314798a70b.zip | |
Fixed hierarchy pass for hierarchies of parametric modules
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index b80f0d493..287f93097 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -152,6 +152,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; cell->type = mod->derive(design, cell->parameters); cell->parameters.clear(); + did_something = true; } if (did_something) |