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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-0320-86/+374
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| * Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Update ABC to git rev 623b5e8Clifford Wolf2019-10-031-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Bump versionClifford Wolf2019-10-031-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
| |\ | | | | | | module->derive() to be lazy and not touch ast if already derived
| | * Fix for svinterfacesEddie Hung2019-09-301-2/+8
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| | * module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
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| * | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-032-6/+50
| |\ \ | | | | | | | | Add -select option to aigmap
| | * | Add quick testEddie Hung2019-09-301-0/+10
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| | * | Add -select option to aigmapEddie Hung2019-09-301-6/+40
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| * | | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-032-27/+56
| |\ \ \ | | | | | | | | | | Add "check -mapped"
| | * | | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Add "check -mapped"Clifford Wolf2019-10-022-21/+36
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16David Shah2019-10-036-2/+184
| |\ \ \ \ | | | | | | | | | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs
| | * | | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | | |/ / | | |/| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wireEddie Hung2019-10-022-0/+32
| |\ \ \ \ | | | | | | | | | | | | RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
| | * | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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| | * | | | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
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| | * | | | Add testEddie Hung2019-09-301-0/+16
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| | * | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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| * | | | log_dump() to support State enumEddie Hung2019-10-023-0/+6
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| * | | | Merge pull request #1428 from YosysHQ/clifford/fixbtorClifford Wolf2019-10-021-6/+9
| |\ \ \ \ | | |_|/ / | |/| | | Fix btor back-end to use "state" instead of "input" for undef init bits
| | * | | Fix btor back-end to use "state" instead of "input" for undef init bitsClifford Wolf2019-10-021-6/+9
| |/ / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #1426 from YosysHQ/mmicko/fix_environMiodrag Milanović2019-10-011-0/+2
| |\ \ \ | | |/ / | |/| | Define environ, fixes #1424
| | * | Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
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| * / Fix typoEddie Hung2019-09-301-1/+1
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* | EnglishEddie Hung2019-10-031-3/+3
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* | More fixesEddie Hung2019-10-011-16/+16
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* | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
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* | No need to punch ports at allEddie Hung2019-09-302-13/+24
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* | Resolve FIXME on calling proc just onceEddie Hung2019-09-301-2/+2
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* | Cleanup $currQ from aigerparseEddie Hung2019-09-301-2/+0
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* | Remove need for $currQ port connectionEddie Hung2019-09-304-114/+129
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* | Add explanation to abc_map.vEddie Hung2019-09-301-0/+16
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* | CleanupEddie Hung2019-09-301-100/+3
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* | Add commentEddie Hung2019-09-301-0/+1
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* | Use a cell_cache to instantiate once rather than opt_merge callEddie Hung2019-09-301-15/+15
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* | scc call on active module module only, plus cleanupEddie Hung2019-09-302-29/+28
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* | Use derived moduleEddie Hung2019-09-301-22/+5
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-3029-132/+1981
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| * Update doc for equiv_optEddie Hung2019-09-301-2/+3
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| * Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-3011-0/+1767
| |\ | | | | | | rpc: new frontend
| | * rpc: new frontend.whitequark2019-09-309-0/+744
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
| | * libs: import json11.whitequark2019-09-303-0/+1023
| | | | | | | | | | | | | | | This commit imports the code from upstream commit dropbox/json11@8ccf1f0c5ecab6151a65f216e7eeccd8588e5457.
| * | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructorsEddie Hung2019-09-301-0/+2
| |\ \ | | | | | | | | Generate Python wrappers for inline constructors
| | * | Generate Python wrappers for inline constructorsBenedikt Tutzer2019-09-231-0/+2
| | | | | | | | | | | | | | | | Fixes: #1353
| * | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-304-6/+10
| |\ \ \ | | | | | | | | | | Open aig frontend as binary file
| | * | | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
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| | * | | Open aig frontend as binary fileMiodrag Milanovic2019-09-294-5/+5
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