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| author | Clifford Wolf <clifford@clifford.at> | 2015-05-18 11:15:49 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-05-18 11:15:49 +0200 |
| commit | 6061b7bd58c2f528f33d1f3859f99a5d0babca21 (patch) | |
| tree | 1990e9a839e0f8a2d3ce5d7ca05bda7ffabbe21a | |
| parent | 83499dc1ba14bc164991be0ee9bdf0ae0a7beff9 (diff) | |
| download | yosys-6061b7bd58c2f528f33d1f3859f99a5d0babca21.tar.gz yosys-6061b7bd58c2f528f33d1f3859f99a5d0babca21.tar.bz2 yosys-6061b7bd58c2f528f33d1f3859f99a5d0babca21.zip | |
bugfix in blif front-end
| -rw-r--r-- | frontends/blif/blifparse.cc | 6 | ||||
| -rw-r--r-- | tests/vloghtb/test_febe.sh | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 4b4ac6098..580fb8647 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -207,10 +207,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name) RTLIL::SigSpec input_sig, output_sig; while ((p = strtok(NULL, " \t\r\n")) != NULL) { RTLIL::Wire *wire; - if (module->wires_.count(stringf("\\%s", p)) > 0) { - wire = module->wires_.at(stringf("\\%s", p)); + if (module->wires_.count(RTLIL::escape_id(p)) > 0) { + wire = module->wires_.at(RTLIL::escape_id(p)); } else { - wire = module->addWire(stringf("\\%s", p)); + wire = module->addWire(RTLIL::escape_id(p)); } input_sig.append(wire); } diff --git a/tests/vloghtb/test_febe.sh b/tests/vloghtb/test_febe.sh index 7756202c4..482d44d9a 100644 --- a/tests/vloghtb/test_febe.sh +++ b/tests/vloghtb/test_febe.sh @@ -6,8 +6,8 @@ source common.sh f=$1 n=$(basename ${f%.v}) -test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f -test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f -test_febe blif "synth; splitnets -ports" ".blif" "write_blif -icells" "read_blif" "-ignore_div_by_zero" $n $f +test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f +test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f +test_febe blif "synth; splitnets -ports" ".blif" "write_blif" "read_blif" "-ignore_div_by_zero" $n $f exit 0 |