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* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-093-122/+120
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09325-1308/+1311
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| * Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| * Intersynth URLClaire Xenia Wolf2021-06-092-2/+2
| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| * Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
| * More deadname stuffClaire Xenia Wolf2021-06-0910-27/+27
| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-0920-26/+26
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-095-422/+422
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-08309-331/+330
| * Add claire deadname stuff to .mailmapClaire Xenia Wolf2021-06-081-0/+4
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-084-13/+41
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-084-5/+94
* | autoname: simple perf optimizationsZachary Snow2021-06-081-11/+15
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* sv: support tasks and functions within packagesZachary Snow2021-06-015-2/+56
* kernel/mem: Recognize some deprecated memory port configs.Marcelina Kościelnicka2021-06-011-0/+10
* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-312-35/+131
* memory_share: Add read port merging.Marcelina Kościelnicka2021-05-291-0/+140
* memory_share: Improve sat-based port sharing.Marcelina Kościelnicka2021-05-281-117/+151
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-285-33/+10
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
* memory_share: Improve same-address merging, recognize wide write ports.Marcelina Kościelnicka2021-05-271-204/+77
* kernel/mem: Add helpers for write port widening.Marcelina Kościelnicka2021-05-272-0/+57
* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-263-26/+32
* kernel/mem: Add prepare_wr_merge helper.Marcelina Kościelnicka2021-05-262-0/+27
* backends/verilog: Try to preserve mem write port priorities.Marcelina Kościelnicka2021-05-261-32/+84
* mem/extract_rdff: Fix "no FF made" edge case.Marcelina Kościelnicka2021-05-252-3/+9
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-255-40/+52
* verilog: fix case expression sign and width handlingZachary Snow2021-05-255-12/+157
* sv: support remaining assignment operatorsZachary Snow2021-05-253-42/+64
* mem/extract_rdff: Add alternate transparency handling.Marcelina Kościelnicka2021-05-251-18/+80
* opt_mem: Add reset/init value support.Marcelina Kościelnicka2021-05-251-0/+12
* kernel/mem: Add model support for read port init value and resets.Marcelina Kościelnicka2021-05-252-4/+73
* mem/extract_rdff: Fix wire naming and wide port support.Marcelina Kościelnicka2021-05-251-6/+22
* memory_bram: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+14
* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-252-0/+62
* kernel/mem: Add emulate_priority helper.Marcelina Kościelnicka2021-05-252-0/+44
* Add memory_narrow pass.Marcelina Kościelnicka2021-05-252-0/+68
* memory_share: Add wide port support.Marcelina Kościelnicka2021-05-251-0/+6
* opt_mem_feedback: Add wide port support.Marcelina Kościelnicka2021-05-251-14/+24
* memory_map: Add wide port support.Marcelina Kościelnicka2021-05-251-16/+17
* sim: Add wide port support.Marcelina Kościelnicka2021-05-251-3/+3
* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-254-2/+35
* kernel/mem: Add a Mem::narrow helper to split up wide ports.Marcelina Kościelnicka2021-05-252-0/+53
* kernel/mem: Emit support for wide ports in packed mode.Marcelina Kościelnicka2021-05-251-30/+34
* kernel/mem: Add model for wide ports.Marcelina Kościelnicka2021-05-252-6/+28
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