| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | Comment to explain separating CREG packing | Eddie Hung | 2019-09-23 | 1 | -0/+8 | |
| | * | | | | | Separate out CREG packing into new pattern, to avoid conflict with PREG | Eddie Hung | 2019-09-23 | 4 | -46/+273 | |
| | * | | | | | Move log_debug("\n") later | Eddie Hung | 2019-09-23 | 1 | -1/+1 | |
| | * | | | | | Move unextend initialisation later | Eddie Hung | 2019-09-23 | 1 | -12/+9 | |
| | * | | | | | Use new port() overload once more | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-23 | 2 | -1/+69 | |
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| | * | | | | | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 | |
| | * | | | | | Use new port/param overload in pmg | Eddie Hung | 2019-09-20 | 4 | -22/+22 | |
| | * | | | | | Output pattern matcher items as log_debug() | Eddie Hung | 2019-09-20 | 2 | -31/+27 | |
| | * | | | | | OPMODE is port not param | Eddie Hung | 2019-09-20 | 1 | -7/+6 | |
| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-20 | 4 | -18/+50 | |
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| | * | | | | | | Do not run xilinx_dsp_cascadeAB for now | Eddie Hung | 2019-09-20 | 1 | -1/+2 | |
| | * | | | | | | WIP for xiinx_dsp_cascadeAB | Eddie Hung | 2019-09-20 | 1 | -3/+499 | |
| | * | | | | | | Run until convergence | Eddie Hung | 2019-09-20 | 1 | -3/+9 | |
| | * | | | | | | Cleanup ice40_dsp.pmg | Eddie Hung | 2019-09-20 | 1 | -12/+6 | |
| | * | | | | | | Cleanup xilinx_dsp | Eddie Hung | 2019-09-20 | 1 | -1/+1 | |
| | * | | | | | | More exceptions | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
| | * | | | | | | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
| | * | | | | | | Update doc | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
| | * | | | | | | Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT | Eddie Hung | 2019-09-20 | 4 | -54/+105 | |
| | * | | | | | | Add an overload for port/param with default value | Eddie Hung | 2019-09-20 | 1 | -0/+8 | |
| | * | | | | | | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 2 | -3/+2 | |
| | * | | | | | | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 | |
| | * | | | | | | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 | |
| | * | | | | | | Small cleanup | Eddie Hung | 2019-09-20 | 1 | -19/+18 | |
| | * | | | | | | Disable support for SB_MAC16 reset since it is async | Eddie Hung | 2019-09-19 | 2 | -3/+7 | |
| | * | | | | | | SB_MAC16 ffCD to not pack same as ffO | Eddie Hung | 2019-09-19 | 1 | -2/+2 | |
| | * | | | | | | Add more complicated macc testcase | Eddie Hung | 2019-09-19 | 2 | -5/+39 | |
| | * | | | | | | Clarify | Eddie Hung | 2019-09-19 | 1 | -1/+2 | |
| | * | | | | | | Update doc for ice40_dsp | Eddie Hung | 2019-09-19 | 1 | -1/+10 | |
| | * | | | | | | Tidy up, fix undriven | Eddie Hung | 2019-09-19 | 1 | -32/+34 | |
| | * | | | | | | Add an index | Eddie Hung | 2019-09-19 | 2 | -0/+3 | |
| | * | | | | | | $__ABC_REG to have WIDTH parameter | Eddie Hung | 2019-09-19 | 2 | -17/+18 | |
| | * | | | | | | Fix DSP48E1 timing by breaking P path if MREG or PREG | Eddie Hung | 2019-09-19 | 4 | -349/+363 | |
| | * | | | | | | Revert "Different approach to timing" | Eddie Hung | 2019-09-19 | 4 | -195/+405 | |
| | * | | | | | | Different approach to timing | Eddie Hung | 2019-09-19 | 4 | -405/+195 | |
| | * | | | | | | Fix width of D | Eddie Hung | 2019-09-19 | 1 | -1/+1 | |
| | * | | | | | | Add mac.sh and macc_tb.v for testing | Eddie Hung | 2019-09-19 | 2 | -0/+99 | |
| | * | | | | | | Suppress $anyseq warnings | Eddie Hung | 2019-09-19 | 1 | -15/+32 | |
| | * | | | | | | Use ID() macro | Eddie Hung | 2019-09-19 | 2 | -210/+210 | |
| | * | | | | | | Use (* techmap_autopurge *) to suppress techmap warnings | Eddie Hung | 2019-09-19 | 2 | -94/+99 | |
| | * | | | | | | D is 25 bits not 24 bits wide | Eddie Hung | 2019-09-19 | 1 | -1/+1 | |
| | * | | | | | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 14 | -95/+723 | |
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| | * | | | | | | | When two boxes connect to each other, need not be a (* keep *) | Eddie Hung | 2019-09-19 | 1 | -6/+1 | |
| | * | | | | | | | Re-enable sign extension for C input | Eddie Hung | 2019-09-19 | 1 | -4/+4 | |
| | * | | | | | | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 | |
| | * | | | | | | | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 | Eddie Hung | 2019-09-19 | 1 | -1/+3 | |
| | * | | | | | | | Do not perform width-checks for DSP48E1 which is much more complicated | Eddie Hung | 2019-09-19 | 1 | -11/+0 | |
| | * | | | | | | | Remove TODO as check should not be necessary | Eddie Hung | 2019-09-19 | 1 | -1/+0 | |
| | * | | | | | | | Revert index to select | Eddie Hung | 2019-09-19 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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