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* Proper write of memory dataMiodrag Milanovic2022-03-111-14/+13
* Start work on memory initMiodrag Milanovic2022-03-091-9/+34
* Fixes and error checkMiodrag Milanovic2022-03-091-1/+5
* cleanupMiodrag Milanovic2022-03-071-1/+2
* Error checks for aiger witnessMiodrag Milanovic2022-03-071-0/+7
* btor2 witness co-simulationMiodrag Milanovic2022-03-071-8/+123
* Bump versiongithub-actions[bot]2022-03-051-1/+1
* Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_idMiodrag Milanović2022-03-042-4/+12
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| * print cell name for properties in yosys-smtbmcN. Engelhardt2022-02-222-4/+12
* | Merge pull request #3206 from YosysHQ/micko/quote_removeMiodrag Milanović2022-03-041-1/+4
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| * | Remove quotes if any from attributeMiodrag Milanovic2022-02-161-1/+4
* | | Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-045-5/+63
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| * | | fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-185-5/+63
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* | | Next dev cycleMiodrag Milanovic2022-03-042-2/+5
* | | Release version 0.15Miodrag Milanovic2022-03-042-3/+3
* | | Update ABCMiodrag Milanovic2022-03-041-1/+1
* | | Update documentationMiodrag Milanovic2022-03-041-1/+96
* | | Merge pull request #3219 from YosysHQ/micko/quick_vcdMiodrag Milanović2022-03-043-0/+21
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| * | | VCD reader support by using external toolMiodrag Milanovic2022-02-283-0/+21
* | | | Merge pull request #3220 from YosysHQ/claire/simstuffMiodrag Milanović2022-03-041-141/+301
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| * | | | Add option to ignore X only signals in outputMiodrag Milanovic2022-03-021-8/+32
| * | | | Write simulation files after simulation is performedMiodrag Milanovic2022-03-021-145/+151
| * | | | Merge pull request #3224 from YosysHQ/micko/refactorClaire Xen2022-03-021-213/+254
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| | * | | | CleanupMiodrag Milanovic2022-03-021-10/+7
| | * | | | Refactor sim output writersMiodrag Milanovic2022-02-281-213/+257
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| * | | | Quick fixMiodrag Milanovic2022-02-281-0/+2
| * | | | Add writing of aiw files to "sim" commandClaire Xenia Wolf2022-02-281-1/+87
| * | | | Hotfix in AIGER witness reader state machineClaire Xenia Wolf2022-02-281-0/+1
* | | | | Bump versiongithub-actions[bot]2022-03-031-1/+1
* | | | | Update CHANGELOGMiodrag Milanovic2022-03-021-0/+12
* | | | | Bump versiongithub-actions[bot]2022-03-011-1/+1
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* | | | Merge pull request #3216 from YosysHQ/claire/simstuffMiodrag Milanović2022-02-282-42/+64
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| * | | Support extended aiw formatMiodrag Milanovic2022-02-271-23/+44
| * | | Fix for last clock edge dataMiodrag Milanovic2022-02-252-3/+2
| * | | Experimental sim changesClaire Xenia Wolf2022-02-251-20/+22
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* | | Bump versiongithub-actions[bot]2022-02-251-1/+1
* | | gowin: Remove unnecessary attributesYRabbit2022-02-241-5/+0
* | | gowin: Add support for true differential outputYRabbit2022-02-241-0/+11
* | | Merge pull request #3211 from YosysHQ/micko/witnessClaire Xen2022-02-222-2/+97
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| * | | Fix cycle 0 in aiger witness co-simulationClaire Xenia Wolf2022-02-181-12/+15
| * | | Changed error messageMiodrag Milanovic2022-02-181-1/+1
| * | | Added AIGER witness file co simulationMiodrag Milanovic2022-02-181-1/+93
* | | | Merge pull request #3197 from YosysHQ/claire/smtbmcfixClaire Xen2022-02-221-1/+4
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| * | | | Add a bit of flexibilty re trace length when processing aiger witnesses in sm...Claire Xenia Wolf2022-02-111-1/+4
* | | | | Bump versiongithub-actions[bot]2022-02-221-1/+1
* | | | | Merge pull request #3203 from YosysHQ/micko/sim_ffMiodrag Milanović2022-02-2145-172/+1170
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| * | | | | Fix handling of ce_over_srstMiodrag Milanovic2022-02-211-3/+2
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| * | | | simplify logic of handling flip-flops and latchesMiodrag Milanovic2022-02-181-118/+42
| * | | | Review cleanupMiodrag Milanovic2022-02-171-6/+5
| * | | | test dlatchsr and adlatchMiodrag Milanovic2022-02-164-4/+94
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