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* Added ezSAT libraryClifford Wolf2013-06-0712-8/+2854
* Renamed opt_rmunused to opt_cleanClifford Wolf2013-06-057-17/+17
* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-031-4/+30
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-024-29/+119
* Fixed techmap/flatten for positional module argumentsClifford Wolf2013-05-261-8/+20
* Improved log messages generated by hierarchy passClifford Wolf2013-05-261-5/+17
* Added -nodetect option to fsm passClifford Wolf2013-05-241-2/+8
* Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.vClifford Wolf2013-05-241-1/+3
* Improved FSM one-hot encoding, added binary encodingClifford Wolf2013-05-243-44/+85
* Added log_assert() apiClifford Wolf2013-05-243-4/+6
* Added log_abort() apiClifford Wolf2013-05-242-1/+3
* Fixed a gcc vs. clang determinism problem in abc passClifford Wolf2013-05-231-4/+11
* Fixed memory corruption bug in opt_rmunusedClifford Wolf2013-05-231-7/+14
* Only initialize TCL interpreter when neededClifford Wolf2013-05-233-39/+50
* Fixed memory leak in ilang frontendClifford Wolf2013-05-231-0/+1
* Added missing newline to some error messagesClifford Wolf2013-05-231-2/+2
* Added labels to "help -write-tex-command-reference-manual" outputClifford Wolf2013-05-231-0/+2
* Added support for processes to show commandClifford Wolf2013-05-231-2/+81
* Fixed show command for constant assignmentsClifford Wolf2013-05-231-2/+2
* Some improvements in opt_rmdffClifford Wolf2013-05-231-2/+33
* Merge pull request #6 from hansiglaser/masterClifford Wolf2013-05-193-4/+19
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| * added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-193-4/+19
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* Removed test cases that have been moved to yosys-test.Clifford Wolf2013-05-1783-18963/+0
* Fixed to aggressive x-folding in opt_constClifford Wolf2013-05-171-8/+21
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-05-161-8/+82
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| * Improved vcdcd.pl (added -d option)Clifford Wolf2013-05-141-8/+82
* | Merge branch 'bugfix'Clifford Wolf2013-05-161-2/+0
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| * Fixed synthesis of functions in latched blocksClifford Wolf2013-05-161-2/+0
* | Some improvements in vcdcd.plClifford Wolf2013-05-141-4/+16
* | Added support for verilog === operatorClifford Wolf2013-05-071-0/+2
* | Added tcl "yosys -import" commandClifford Wolf2013-05-021-3/+29
* | Improved/simplified TCL bindingsClifford Wolf2013-05-013-40/+57
* | Added support for const cell inputs in techmapClifford Wolf2013-04-271-6/+28
* | Fixed README for new show command behavior (svg vs. ps)Clifford Wolf2013-04-271-2/+6
* | Added "flatten" passClifford Wolf2013-04-261-1/+41
* | Fixed handling of positional module parametersClifford Wolf2013-04-261-6/+4
* | Fixed hierarchy pass for hierarchies of parametric modulesClifford Wolf2013-04-261-0/+1
* | Only use sha1 checksums for names of parametric modules when the verbose form...Clifford Wolf2013-04-261-9/+20
* | Fixed "show -format ..." command line parsingClifford Wolf2013-04-151-1/+1
* | Added "submod -name ..." supportClifford Wolf2013-04-151-40/+96
* | Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-132-4/+23
* | Fixed a bug in opt_const when optimizing 1-bit compares with constantsClifford Wolf2013-04-131-2/+4
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-04-071-8/+40
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| * \ Merge pull request #5 from hansiglaser/masterClifford Wolf2013-04-051-6/+23
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| | * | fsm_export: optionally use binary state encoding as state names instead ofJohann Glaser2013-04-051-6/+23
| * | | Merge pull request #4 from hansiglaser/masterClifford Wolf2013-04-051-5/+20
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| | * | fsm_export: specify KISS filename on command lineJohann Glaser2013-04-051-5/+20
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* / / Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-071-4/+4
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* | Fixed/improved handling of colored wires in show commandClifford Wolf2013-04-011-2/+2
* | Added support for @<set-name> in expand select ops (%x, %ci, %co)Clifford Wolf2013-04-011-2/+12
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