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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-2220-34/+29
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-223-94/+18
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-2262-800/+800
* SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad...Clifford Wolf2014-07-222-152/+158
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-2262-951/+954
* Fixed ilang parsing of process attributesClifford Wolf2014-07-221-0/+1
* Fixed make rules for ilang parserClifford Wolf2014-07-221-1/+3
* Use "opt -fine" in test/vloght/test_mapopt.shClifford Wolf2014-07-212-2/+3
* Added "opt_const -keepdc"Clifford Wolf2014-07-212-15/+168
* Added mul to mux conversion to "opt_const -fine"Clifford Wolf2014-07-211-0/+55
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-214-16/+145
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-213-26/+24
* Added opt_const support for simple identitiesClifford Wolf2014-07-211-0/+69
* Various improvements in test/vloghtbClifford Wolf2014-07-214-30/+52
* Added support for scripts with labelsClifford Wolf2014-07-211-11/+74
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-214-25/+22
* Removed deprecated module->new_wire()Clifford Wolf2014-07-2111-56/+47
* Wider range of cell types supported in "share" passClifford Wolf2014-07-213-36/+249
* Bugfix in satgen for cells with wider in- than outputs.Clifford Wolf2014-07-211-1/+9
* Added module->remove(), module->addWire(), module->addCell(), cell->check()Clifford Wolf2014-07-212-8/+44
* Added log_ping()Clifford Wolf2014-07-211-0/+1
* Use ezSAT::non_incremental() in "share" passClifford Wolf2014-07-211-0/+2
* Added ezSAT::keep_cnf() and ezSAT::non_incremental()Clifford Wolf2014-07-215-8/+71
* Fixed ezSAT stand-alone buildClifford Wolf2014-07-212-8/+4
* Updated minisatClifford Wolf2014-07-2120-45/+45
* Using relative path names in minisat headersClifford Wolf2014-07-211-1/+1
* Added yet another resource sharing test caseClifford Wolf2014-07-202-0/+49
* Added support for resource sharing in mux control logicClifford Wolf2014-07-201-86/+155
* Added "select -assert-count"Clifford Wolf2014-07-201-6/+43
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-203-8/+3
* Improved tests/share/generate.pyClifford Wolf2014-07-201-2/+12
* Fixed creation of shift supercells in "share" passClifford Wolf2014-07-201-4/+20
* Small fix in tests/vloghtb/run-test.shClifford Wolf2014-07-201-0/+2
* Activated tests/share in "make test"Clifford Wolf2014-07-201-0/+1
* Added "miter -equiv -flatten"Clifford Wolf2014-07-202-2/+15
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-204-16/+37
* Added tests/vloghtb/test_share.shClifford Wolf2014-07-205-1/+57
* Added tests/share for testing "share" supercell creationClifford Wolf2014-07-203-0/+58
* Added "share" supercell creationClifford Wolf2014-07-201-1/+115
* Added removing of always inactive cells to "share" passClifford Wolf2014-07-201-8/+42
* Progress in "share" passClifford Wolf2014-07-201-112/+185
* Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversionClifford Wolf2014-07-202-3/+11
* Added SIZE() macroClifford Wolf2014-07-201-0/+2
* Added log_cell()Clifford Wolf2014-07-202-0/+17
* Progress in "share" passClifford Wolf2014-07-201-19/+56
* Added tests/vloghtbClifford Wolf2014-07-202-0/+18
* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-201-17/+21
* Added support for $bu0 to verilog backendClifford Wolf2014-07-201-0/+16
* Started to implement real resource sharingClifford Wolf2014-07-192-0/+444
* Fixed log_id() memory corruptionClifford Wolf2014-07-192-5/+10