iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added per-pass cpu usage statistics	Clifford Wolf	2014-08-01	4	-12/+86
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	9	-30/+170
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*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	2	-10/+14
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*	Consolidated hana test benches into fewer files	Clifford Wolf	2014-08-01	175	-1332/+1622
\| \| \| \| \| \| \| \|	for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module ", sprintf("module f%d_",ARGIND)); print; }' \ ${pf}__test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done; ..etc..
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	2	-11/+32
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*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	3	-12/+14
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*	Various cleanups in Makefile, Renamed default configurations	Clifford Wolf	2014-07-31	1	-21/+12
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*	Added compiler + compiler version + compiler flags to version string	Clifford Wolf	2014-07-31	1	-1/+2
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*	Fixed build of verific bindings	Clifford Wolf	2014-07-31	1	-11/+11
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	46	-1059/+1086
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*	Added "trace" command	Clifford Wolf	2014-07-31	4	-2/+103
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*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	2	-96/+97
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	15	-44/+142
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	41	-665/+790
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	9	-12/+15
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31	2	-14/+43
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*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31	1	-747/+590
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*	Added "yosys -A"	Clifford Wolf	2014-07-31	1	-1/+10
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*	Added "yosys -Q"	Clifford Wolf	2014-07-31	1	-26/+35
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	3	-12/+126
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*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30	2	-4/+4
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*	Added write_file command	Clifford Wolf	2014-07-30	4	-5/+84
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*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30	7	-22/+39
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*	Improvements in test_cell	Clifford Wolf	2014-07-30	1	-35/+89
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*	New techmap default rules for $shr $sshr $shl $sshl	Clifford Wolf	2014-07-30	1	-282/+62
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*	Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models	Clifford Wolf	2014-07-30	1	-36/+39
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*	Added native support for shift operations to ezSAT	Clifford Wolf	2014-07-30	2	-1/+95
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*	Added "log_dump_val_worker(char *v)"	Clifford Wolf	2014-07-30	1	-0/+1
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*	Added CodingStyle document	Clifford Wolf	2014-07-30	1	-0/+43
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*	Added "kernel/yosys.h" and "kernel/yosys.cc"	Clifford Wolf	2014-07-30	8	-61/+133
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*	Added "test_cell" command	Clifford Wolf	2014-07-29	3	-1/+186
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	5	-10/+12
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*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
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*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29	1	-5/+6
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*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29	1	-1/+3
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	4	-10/+29
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	12	-40/+214
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*	Removed left over debug code	Clifford Wolf	2014-07-28	2	-2/+0
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*	Fixed part selects of parameters	Clifford Wolf	2014-07-28	2	-7/+31
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*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28	1	-5/+31
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*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28	1	-2/+2
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*	Fixed width detection for part selects	Clifford Wolf	2014-07-28	1	-2/+2
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*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	6	-22/+96
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	6	-2/+13
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	52	-251/+236
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*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	2	-0/+15
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*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28	1	-0/+22
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*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28	1	-0/+1
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*	Improvements in tests/vloghtb	Clifford Wolf	2014-07-28	2	-11/+17
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*	Added techmap -extern	Clifford Wolf	2014-07-27	3	-17/+92
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