| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into eddie/muxpack | Eddie Hung | 2019-06-10 | 3 | -13/+72 |
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| | * | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
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| | * | Merge pull request #1082 from corecode/u4k | David Shah | 2019-06-10 | 1 | -0/+24 |
| | |\ | | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | ||||
| | | * | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+24 |
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| | * | Merge pull request #1078 from YosysHQ/eddie/muxcover_costs | Clifford Wolf | 2019-06-08 | 1 | -12/+42 |
| | |\ | | | | | | | Allow muxcover costs to be changed | ||||
| | | * | Allow muxcover costs to be changed | Eddie Hung | 2019-06-07 | 1 | -12/+42 |
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| * | | | Merge branch 'master' into eddie/muxpack | Eddie Hung | 2019-06-07 | 39 | -364/+573 |
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| | * | | Fix spacing from spaces to tabs | Eddie Hung | 2019-06-07 | 1 | -362/+362 |
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| | * | | Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger | Clifford Wolf | 2019-06-07 | 27 | -45/+128 |
| | |\ \ | | | | | | | | | Fix read_aiger to really get tested, and fix some uncovered read_aiger issues | ||||
| | | * | | Add read_aiger to CHANGELOG | Eddie Hung | 2019-06-07 | 1 | -0/+1 |
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| | | * | | Fix spacing (entire file is wrong anyway, will fix later) | Eddie Hung | 2019-06-07 | 1 | -3/+3 |
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| | | * | | Remove unnecessary std::getline() for ASCII | Eddie Hung | 2019-06-07 | 1 | -3/+0 |
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| | | * | | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
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| | | * | | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 |
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| | | * | | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 |
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| | | * | | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
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| | | * | | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 |
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| | * | | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 9 | -3/+93 |
| | |\ \ | | | | | | | | | elaboration system tasks | ||||
| | | * | | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 4 | -50/+38 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | * | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 10 | -5/+107 |
| | | |\ \ | | | | | | | | | | | | | | | | clifford/pr983 | ||||
| | | | * | | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 10 | -5/+107 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | ||||
| | * | | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 |
| | |/ / / | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Merge branch 'tux3-implicit_named_connection' | Clifford Wolf | 2019-06-07 | 4 | -3/+40 |
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| | | * | | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 3 | -13/+2 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | * | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵ | Clifford Wolf | 2019-06-07 | 5 | -4/+52 |
| | | |\ \ \ | | | |_|/ | | |/| | | | | | | | into tux3-implicit_named_connection | ||||
| | | | * | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 5 | -12/+59 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. | ||||
| | * | | | | Merge pull request #1076 from thasti/centos7-build-fix | Clifford Wolf | 2019-06-07 | 1 | -1/+0 |
| | |\ \ \ \ | | |/ / / | |/| | | | Fix pyosys-build on CentOS7 | ||||
| | | * | | | remove boost/log/exceptions.hpp from wrapper generator | Stefan Biereigel | 2019-06-07 | 1 | -1/+0 |
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| * | | | | Comment O(N) -> O(N^2) | Eddie Hung | 2019-06-07 | 1 | -1/+1 |
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| * | | | | Add nonexcl case test, comment out two others | Eddie Hung | 2019-06-07 | 2 | -22/+57 |
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| * | | | | Extend ExclusiveDatabase to query SigSpec-s (for $pmux) | Eddie Hung | 2019-06-07 | 1 | -19/+27 |
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| * | | | | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results | Eddie Hung | 2019-06-07 | 1 | -1/+64 |
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| * | | | | Add @cliffordwolf freduce testcase | Eddie Hung | 2019-06-07 | 2 | -0/+30 |
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| * | | | | Add nonexclusive test from @cliffordwolf | Eddie Hung | 2019-06-07 | 2 | -0/+28 |
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| * | | | | Resolve @cliffordwolf comment on redundant check | Eddie Hung | 2019-06-07 | 1 | -10/+2 |
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| * | | | | Resolve @cliffordwolf comment on sigmap | Eddie Hung | 2019-06-07 | 1 | -2/+2 |
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| * | | | | Another muxpack test | Eddie Hung | 2019-06-07 | 2 | -0/+32 |
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| * | | | | Fix and test for balanced case | Eddie Hung | 2019-06-06 | 3 | -10/+55 |
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| * | | | | Fix warnings | Eddie Hung | 2019-06-06 | 2 | -3/+3 |
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| * | | | | Support cascading $pmux.A with $mux.A and $mux.B | Eddie Hung | 2019-06-06 | 3 | -17/+65 |
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| * | | | | More cleanup | Eddie Hung | 2019-06-06 | 1 | -15/+20 |
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| * | | | | Fix spacing | Eddie Hung | 2019-06-06 | 1 | -6/+5 |
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| * | | | | Non chain user check using next_sig | Eddie Hung | 2019-06-06 | 1 | -7/+5 |
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| * | | | | Add non exclusive test | Eddie Hung | 2019-06-06 | 2 | -0/+56 |
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| * | | | | Move muxpack from passes/techmap to passes/opt | Eddie Hung | 2019-06-06 | 3 | -1/+1 |
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| * | | | | Update doc | Eddie Hung | 2019-06-06 | 1 | -4/+5 |
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| * | | | | Add to CHANGELOG | Eddie Hung | 2019-06-06 | 1 | -0/+1 |
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| * | | | | One more and tidy up | Eddie Hung | 2019-06-06 | 2 | -6/+28 |
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| * | | | | Add a few more special case tests | Eddie Hung | 2019-06-06 | 2 | -0/+51 |
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| * | | | | Add tests, fix for != | Eddie Hung | 2019-06-06 | 3 | -9/+110 |
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index : iCE40/yosys | |
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