| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 | |
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| | | * | | | | | | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
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| | | * | | | | | | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 58 | -598/+1321 | |
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| | | * | | | | | | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
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| | | * | | | | | | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
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| | | * | | | | | | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
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| | | * | | | | | | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
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| | * | | | | | | | | | | Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg | Clifford Wolf | 2019-08-22 | 2 | -0/+17 | |
| | |\ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|/ | | |/| | | | | | | | | mem2reg to preserve user attributes and src | |||||
| | | * | | | | | | | | | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| | * | | | | | | | | | Merge pull request #1315 from mmicko/fix_dependencies | whitequark | 2019-08-21 | 1 | -1/+1 | |
| | |\ \ \ \ \ \ \ \ \ | | |/ / / / / / / / | |/| | | | | | | | | Fix test_pmgen deps | |||||
| | | * | | | | | | | | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | | | | Use semicolon | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | | | | techmap before read | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-21 | 0 | -0/+0 | |
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| | * | | | | | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 4 | -4/+21 | |
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | techmap -max_iter to apply to each module individually | |||||
| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-21 | 2 | -2/+2 | |
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| | * | | | | | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | * | | | | | | | | | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | | | | | Output "h" extension only if boxes | Eddie Hung | 2019-08-21 | 1 | -28/+32 | |
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| * | | | | | | | | | | Revert "Fix omode which inserts an output if none exists (otherwise abc9 ↵ | Eddie Hung | 2019-08-21 | 1 | -8/+7 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | breaks)" This reverts commit 8182cb9d91555d5be52abbfeeb5d22af05342d8a. | |||||
| * | | | | | | | | | | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 | |
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| * | | | | | | | | | | Fix omode which inserts an output if none exists (otherwise abc9 breaks) | Eddie Hung | 2019-08-20 | 1 | -7/+8 | |
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| * | | | | | | | | | | Revert "Only xaig if GetSize(output_bits) > 0" | Eddie Hung | 2019-08-20 | 1 | -149/+147 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7b646101e936cacd20938c20ddfbaa63ee268fb2. | |||||
| * | | | | | | | | | | Only xaig if GetSize(output_bits) > 0 | Eddie Hung | 2019-08-20 | 1 | -147/+149 | |
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| * | | | | | | | | | | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | | | | | Merge branch 'eddie/fix_techmap' into xaig_arrival | Eddie Hung | 2019-08-20 | 4 | -1/+16 | |
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| | * | | | | | | | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | * | | | | | | | | | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 | |
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| | * | | | | | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
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| * | | | | | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
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| * | | | | | | | | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 6 | -171/+26 | |
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| * | | | | | | | | | ecp5: remove DPR16X4 from abc_unmap.v | Eddie Hung | 2019-08-20 | 1 | -20/+0 | |
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| * | | | | | | | | | ecp5 to use -max_iter 1 | Eddie Hung | 2019-08-20 | 3 | -4/+3 | |
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| * | | | | | | | | | ecp5 to use abc_map.v and _unmap.v | Eddie Hung | 2019-08-20 | 7 | -14/+89 | |
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| * | | | | | | | | | Add (* abc_arrival=<int> *) doc | Eddie Hung | 2019-08-20 | 1 | -0/+5 | |
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| * | | | | | | | | | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 | |
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| * | | | | | | | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 9 | -730/+68 | |
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| * | | | | | | | | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 | |
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| * | | | | | | | | | retime_mode -> dff_mode | Eddie Hung | 2019-08-20 | 1 | -7/+7 | |
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| * | | | | | | | | | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 | |
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| * | | | | | | | | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 | |
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| * | | | | | | | | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 | |
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| * | | | | | | | | | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 | |
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| * | | | | | | | | | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 5 | -16/+23 | |
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| | * | | | | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 5 | -16/+23 | |
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | [WIP] synth xilinx renaming, as per #1184 | |||||
| | | * \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 191 | -4502/+7003 | |
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| | | * | | | | | | | | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 | |
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| | | * | | | | | | | | | Update changelog | Eddie Hung | 2019-07-22 | 1 | -3/+4 | |
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| | | * | | | | | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
| aboutsummaryrefslogtreecommitdiffstats |