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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:14:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:14:40 -0700 |
| commit | bbab6086918f8af3a8a09c2be56208fc29ef7068 (patch) | |
| tree | 378ddd9860014548bee29a57d5eb285fa75b244d | |
| parent | fad15d276dd9746b41a2d3e1592285ad4362fe21 (diff) | |
| download | yosys-bbab6086918f8af3a8a09c2be56208fc29ef7068.tar.gz yosys-bbab6086918f8af3a8a09c2be56208fc29ef7068.tar.bz2 yosys-bbab6086918f8af3a8a09c2be56208fc29ef7068.zip | |
Remove SRL* delays from cells_sim.v
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index e5261de1c..1ab718ccc 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -342,8 +342,7 @@ module RAM128X1D ( endmodule module SRL16E ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output Q, + output Q, input A0, A1, A2, A3, CE, CLK, D ); parameter [15:0] INIT = 16'h0000; @@ -361,9 +360,8 @@ module SRL16E ( endmodule module SRLC32E ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output Q, - (* abc_arrival=1114 *) output Q31, + output Q, + output Q31, input [4:0] A, input CE, CLK, D ); |