| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | | smtio: Emit `mode: start` options before `set-logic` command and any other op... | Alberto Gonzalez | 2020-07-20 | 1 | -1/+8 |
| | * | | | smtio: Add support for parsing `yosys-smt2-solver-option` info statements. | Alberto Gonzalez | 2020-07-20 | 1 | -3/+10 |
| | * | | | qbfsat: Add `-solver-option` option. | Alberto Gonzalez | 2020-07-20 | 2 | -1/+15 |
| | * | | | smt2: Add `-solver-option` option. | Alberto Gonzalez | 2020-07-20 | 1 | -0/+13 |
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| * | | | Merge pull request #2282 from YosysHQ/claire/satunsat | clairexen | 2020-07-20 | 2 | -4/+4 |
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| | * | | | Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc | Claire Wolf | 2020-07-20 | 2 | -4/+4 |
| * | | | | celltypes: Fix EN port name for some FF types. | Marcelina Kościelnicka | 2020-07-20 | 1 | -4/+4 |
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| * | | | Merge pull request #2276 from YosysHQ/mwk/satgen-cc | clairexen | 2020-07-20 | 3 | -1166/+1190 |
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| | * | | satgen: Move importCell out of the header. | Marcelina Kościelnicka | 2020-07-19 | 3 | -1166/+1190 |
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| * | | Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix | Miodrag Milanović | 2020-07-17 | 1 | -2/+6 |
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| | * | | sf2: Emit CLKINT even if -clkbuf not passed | Marcelina Kościelnicka | 2020-07-17 | 1 | -2/+6 |
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| * | | Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix | Miodrag Milanović | 2020-07-17 | 1 | -12/+12 |
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| | * | | anlogic: Fix FF mapping. | Marcelina Kościelnicka | 2020-07-17 | 1 | -12/+12 |
| * | | | Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs | clairexen | 2020-07-16 | 4 | -214/+135 |
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| | * | | | sf2: replace sf2_iobs with {clkbuf,iopad}map | Dan Ravensloft | 2020-07-09 | 4 | -214/+135 |
| * | | | | Merge pull request #2273 from whitequark/write-verilog-always-star-initial | clairexen | 2020-07-16 | 1 | -0/+5 |
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| | * | | | verilog_backend: in non-SV mode, add a trigger for `always @*`. | whitequark | 2020-07-16 | 1 | -0/+5 |
| * | | | | Merge pull request #2272 from whitequark/write-verilog-sv | clairexen | 2020-07-16 | 2 | -11/+20 |
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| | * | | | verilog_backend: add `-sv` option, make `-o <filename>.sv` work. | whitequark | 2020-07-16 | 2 | -11/+20 |
| * | | | | Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic | Miodrag Milanović | 2020-07-16 | 4 | -62/+49 |
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| | * | | | | anlogic: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-14 | 4 | -62/+49 |
| * | | | | | Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf | Miodrag Milanović | 2020-07-16 | 5 | -122/+11 |
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| | * | | | | | efinix: Nuke efinix_gbuf in favor of clkbufmap. | Marcelina Kościelnicka | 2020-07-04 | 5 | -122/+11 |
| * | | | | | | Merge pull request #2270 from whitequark/cxxrtl-fix-typo | whitequark | 2020-07-16 | 1 | -1/+1 |
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| | * | | | | | | cxxrtl: fix typo. NFC. | whitequark | 2020-07-14 | 1 | -1/+1 |
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| * | | | | | | Merge pull request #2269 from YosysHQ/claire/bisonwall | whitequark | 2020-07-15 | 2 | -64/+57 |
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| | * | | | | | | Treat all bison warnings as errors in verilog front-end | Claire Wolf | 2020-07-15 | 1 | -1/+1 |
| | * | | | | | | Use %precedence in verilog_parser.y | Claire Wolf | 2020-07-15 | 1 | -4/+4 |
| | * | | | | | | Fix bison warnings for missing %empty | Claire Wolf | 2020-07-15 | 1 | -59/+52 |
| | * | | | | | | Run bison with -Wall for verilog front-end | Claire Wolf | 2020-07-15 | 1 | -1/+1 |
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| * | | | | | | Merge pull request #2257 from antmicro/fix-conflicts | clairexen | 2020-07-15 | 5 | -9/+59 |
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| | * | | | | | | Add missing semicolons | Kamil Rakoczy | 2020-07-15 | 1 | -5/+5 |
| | * | | | | | | Fix S/R conflicts | Kamil Rakoczy | 2020-07-10 | 1 | -1/+2 |
| | * | | | | | | Fix R/R conflicts | Kamil Rakoczy | 2020-07-10 | 1 | -10/+1 |
| | * | | | | | | Revert "Revert PRs #2203 and #2244." | Kamil Rakoczy | 2020-07-10 | 5 | -10/+68 |
| * | | | | | | | opt_merge: Dedup one more use of FF cell type list. | Marcelina Kościelnicka | 2020-07-15 | 1 | -3/+1 |
| * | | | | | | | achronix: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-14 | 1 | -1/+1 |
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| * | | | | | | intel: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-13 | 8 | -178/+17 |
| * | | | | | | Revert "intel_alm: direct M10K instantiation" | Lofty | 2020-07-13 | 8 | -128/+38 |
| * | | | | | | Merge pull request #2263 from whitequark/cxxrtl-capi-eval-commit | whitequark | 2020-07-13 | 2 | -0/+20 |
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| | * | | | | | | cxxrtl: expose eval() and commit() via the C API. | whitequark | 2020-07-12 | 2 | -0/+20 |
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| * | | | | | | xilinx: Fix srl regression. | Marcelina Kościelnicka | 2020-07-12 | 2 | -2/+43 |
| * | | | | | | proc_dlatch: Remove init values for combinatorial processes. | Marcelina Kościelnicka | 2020-07-12 | 1 | -0/+33 |
| * | | | | | | dfflegalize: Gather init values from all wires. | Marcelina Kościelnicka | 2020-07-12 | 1 | -1/+1 |
| * | | | | | | Merge pull request #2256 from YosysHQ/claire/fix2241 | clairexen | 2020-07-10 | 1 | -0/+2 |
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| | * | | | | | Add AST_EDGE support to AstNode::detect_latch(), fixes #2241 | Claire Wolf | 2020-07-10 | 1 | -0/+2 |
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| * | | | | | Merge pull request #2255 from whitequark/bison-Werror-conflicts | whitequark | 2020-07-09 | 6 | -69/+11 |
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| | * | | | | | verilog_parser: turn S/R and R/R conflicts into hard errors. | whitequark | 2020-07-09 | 1 | -1/+1 |
| | * | | | | | Revert PRs #2203 and #2244. | whitequark | 2020-07-09 | 5 | -68/+10 |
| * | | | | | | Merge pull request #2254 from whitequark/cxxrtl-extern-c | whitequark | 2020-07-09 | 1 | -0/+1 |
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