| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #3206 from YosysHQ/micko/quote_remove | Miodrag Milanović | 2022-03-04 | 1 | -1/+4 |
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| | * | Remove quotes if any from attribute | Miodrag Milanovic | 2022-02-16 | 1 | -1/+4 |
| * | | Merge pull request #3207 from nakengelhardt/json_escape_quotes | Miodrag Milanović | 2022-03-04 | 5 | -5/+63 |
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| | * | | fix handling of escaped chars in json backend and frontend | N. Engelhardt | 2022-02-18 | 5 | -5/+63 |
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| * | | Next dev cycle | Miodrag Milanovic | 2022-03-04 | 2 | -2/+5 |
| * | | Release version 0.15 | Miodrag Milanovic | 2022-03-04 | 2 | -3/+3 |
| * | | Update ABC | Miodrag Milanovic | 2022-03-04 | 1 | -1/+1 |
| * | | Update documentation | Miodrag Milanovic | 2022-03-04 | 1 | -1/+96 |
| * | | Merge pull request #3219 from YosysHQ/micko/quick_vcd | Miodrag Milanović | 2022-03-04 | 3 | -0/+21 |
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| | * | | VCD reader support by using external tool | Miodrag Milanovic | 2022-02-28 | 3 | -0/+21 |
| * | | | Merge pull request #3220 from YosysHQ/claire/simstuff | Miodrag Milanović | 2022-03-04 | 1 | -141/+301 |
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| | * | | | Add option to ignore X only signals in output | Miodrag Milanovic | 2022-03-02 | 1 | -8/+32 |
| | * | | | Write simulation files after simulation is performed | Miodrag Milanovic | 2022-03-02 | 1 | -145/+151 |
| | * | | | Merge pull request #3224 from YosysHQ/micko/refactor | Claire Xen | 2022-03-02 | 1 | -213/+254 |
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| | | * | | | Cleanup | Miodrag Milanovic | 2022-03-02 | 1 | -10/+7 |
| | | * | | | Refactor sim output writers | Miodrag Milanovic | 2022-02-28 | 1 | -213/+257 |
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| | * | | | Quick fix | Miodrag Milanovic | 2022-02-28 | 1 | -0/+2 |
| | * | | | Add writing of aiw files to "sim" command | Claire Xenia Wolf | 2022-02-28 | 1 | -1/+87 |
| | * | | | Hotfix in AIGER witness reader state machine | Claire Xenia Wolf | 2022-02-28 | 1 | -0/+1 |
| * | | | | Bump version | github-actions[bot] | 2022-03-03 | 1 | -1/+1 |
| * | | | | Update CHANGELOG | Miodrag Milanovic | 2022-03-02 | 1 | -0/+12 |
| * | | | | Bump version | github-actions[bot] | 2022-03-01 | 1 | -1/+1 |
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| * | | | Merge pull request #3216 from YosysHQ/claire/simstuff | Miodrag Milanović | 2022-02-28 | 2 | -42/+64 |
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| | * | | Support extended aiw format | Miodrag Milanovic | 2022-02-27 | 1 | -23/+44 |
| | * | | Fix for last clock edge data | Miodrag Milanovic | 2022-02-25 | 2 | -3/+2 |
| | * | | Experimental sim changes | Claire Xenia Wolf | 2022-02-25 | 1 | -20/+22 |
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| * | | Bump version | github-actions[bot] | 2022-02-25 | 1 | -1/+1 |
| * | | gowin: Remove unnecessary attributes | YRabbit | 2022-02-24 | 1 | -5/+0 |
| * | | gowin: Add support for true differential output | YRabbit | 2022-02-24 | 1 | -0/+11 |
| * | | Merge pull request #3211 from YosysHQ/micko/witness | Claire Xen | 2022-02-22 | 2 | -2/+97 |
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| | * | | Fix cycle 0 in aiger witness co-simulation | Claire Xenia Wolf | 2022-02-18 | 1 | -12/+15 |
| | * | | Changed error message | Miodrag Milanovic | 2022-02-18 | 1 | -1/+1 |
| | * | | Added AIGER witness file co simulation | Miodrag Milanovic | 2022-02-18 | 1 | -1/+93 |
| * | | | Merge pull request #3197 from YosysHQ/claire/smtbmcfix | Claire Xen | 2022-02-22 | 1 | -1/+4 |
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| | * | | | Add a bit of flexibilty re trace length when processing aiger witnesses in sm... | Claire Xenia Wolf | 2022-02-11 | 1 | -1/+4 |
| * | | | | Bump version | github-actions[bot] | 2022-02-22 | 1 | -1/+1 |
| * | | | | Merge pull request #3203 from YosysHQ/micko/sim_ff | Miodrag Milanović | 2022-02-21 | 45 | -172/+1170 |
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| | * | | | | Fix handling of ce_over_srst | Miodrag Milanovic | 2022-02-21 | 1 | -3/+2 |
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| | * | | | simplify logic of handling flip-flops and latches | Miodrag Milanovic | 2022-02-18 | 1 | -118/+42 |
| | * | | | Review cleanup | Miodrag Milanovic | 2022-02-17 | 1 | -6/+5 |
| | * | | | test dlatchsr and adlatch | Miodrag Milanovic | 2022-02-16 | 4 | -4/+94 |
| | * | | | Added test cases | Miodrag Milanovic | 2022-02-16 | 39 | -0/+897 |
| | * | | | Add support for various ff/latch cells simulation | Miodrag Milanovic | 2022-02-16 | 3 | -169/+258 |
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| * / | | ecp5: Do not use specify in generate in cells_sim.v. | Marcelina Kościelnicka | 2022-02-21 | 1 | -28/+15 |
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| * | | Bump version | github-actions[bot] | 2022-02-16 | 1 | -1/+1 |
| * | | Merge pull request #3204 from YosysHQ/claire/update-abc | Miodrag Milanović | 2022-02-15 | 1 | -1/+1 |
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| | * | | Bump ABC version | Miodrag Milanovic | 2022-02-15 | 1 | -1/+1 |
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| * | | Bump version | github-actions[bot] | 2022-02-15 | 1 | -1/+1 |
| * | | verilog: support for time scale delay values | Zachary Snow | 2022-02-14 | 4 | -4/+42 |
| * | | Fix access to whole sub-structs (#3086) | Kamil Rakoczy | 2022-02-14 | 7 | -11/+72 |
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